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[188.155.181.108]) by smtp.gmail.com with ESMTPSA id d25sm7386899ejz.4.2022.02.23.03.34.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Feb 2022 03:34:56 -0800 (PST) Message-ID: <498e89dd-c438-68dc-69b5-8de82045ffbd@canonical.com> Date: Wed, 23 Feb 2022 12:34:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v9 05/10] dt-bindings: clock: Add bindings for SP7021 clock driver Content-Language: en-US To: Qin Jian , robh+dt@kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, broonie@kernel.org, arnd@arndb.de, stefan.wahren@i2se.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, wells.lu@sunplus.com, Rob Herring References: <2089471296584b527f1e08f51f5216d1e733741f.1645413746.git.qinjian@cqplus1.com> From: Krzysztof Kozlowski In-Reply-To: <2089471296584b527f1e08f51f5216d1e733741f.1645413746.git.qinjian@cqplus1.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 21/02/2022 04:29, Qin Jian wrote: > Add documentation to describe Sunplus SP7021 clock driver bindings. > > Reviewed-by: Stephen Boyd > Reviewed-by: Rob Herring > Signed-off-by: Qin Jian > --- > .../bindings/clock/sunplus,sp7021-clkc.yaml | 52 ++++++++ > MAINTAINERS | 2 + > include/dt-bindings/clock/sp-sp7021.h | 112 ++++++++++++++++++ > 3 files changed, 166 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml > create mode 100644 include/dt-bindings/clock/sp-sp7021.h > > diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml > new file mode 100644 > index 000000000..e6d098cf4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) Sunplus Co., Ltd. 2021 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sunplus SP7021 SoC Clock Controller Binding > + > +maintainers: > + - Qin Jian > + > +properties: > + compatible: > + const: sunplus,sp7021-clkc > + > + "#clock-cells": > + const: 1 > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: External oscillator clock > + - description: System clock > + > + clock-names: > + items: > + - const: extclk > + - const: pllsys > + > +required: > + - compatible > + - "#clock-cells" > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + clkc: clock-controller@9c000000 { > + compatible = "sunplus,sp7021-clkc"; > + #clock-cells = <1>; > + reg = <0x9c000000 0x280>; > + clocks = <&extclk>, <&clkc PLL_SYS>; Except the warning pointed out by Rob's bot, it looks like you feed this clock-controller with a clock from itself. Is there a point to express it in DTS at all? > + clock-names = "extclk", "pllsys"; > + }; Best regards, Krzysztof