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bits=128/128); Mon, 06 Jul 2026 05:47:43 -0700 (PDT) Message-ID: <4bf121e6-ff38-4acd-8fe9-11489b54bf55@oss.qualcomm.com> Date: Mon, 6 Jul 2026 14:47:40 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 5/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support To: Qiang Yu , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com> <20260702-tcsr_qref_0702-v7-5-776f2811b7af@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260702-tcsr_qref_0702-v7-5-776f2811b7af@oss.qualcomm.com> Content-Type: text/plain; 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26+5WarGzCASEmmIJs8vhDdQ8sRFm0KNfRsizYptnYhO/Bum4V8pjDyOUkB0nZ10GlbiJrHcXQr 0MnvUztJsvNW6TOTtD8LwvDVrJAYhoe8Ut8JUc9RISaQhcu6EB5TuPVmC0sWEQdIn3ZuzuuCBdn vYk7QPPbjXi1KWEwpA/yTEggRMXx2qJYlBPD5l4pXgw1MT5mvx4XfvumSJoIL/Iqmd8DZI94LBX 6mK1BmBHJi0IBLZIWxA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_01,2026-07-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060129 On 7/2/26 9:36 AM, Qiang Yu wrote: > Mahua is based on Glymur but uses a different QREF topology, requiring > distinct regulator lists and clock descriptors for its PCIe clock > references. > > Add mahua-specific regulator arrays and clk descriptor table, and use > match_data to select the correct descriptor table per compatible string at > probe time. > > Signed-off-by: Qiang Yu > --- [...] > +static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = { > + [TCSR_EDP_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { OK > + .name = "tcsr_edp_clkref_en", > + .offset = 0x60, > + .regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators), > + }, > + [TCSR_PCIE_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (PCIe4) OK > + .name = "tcsr_pcie_2_clkref_en", > + .offset = 0x4c, > + .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), > + }, > + [TCSR_PCIE_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (PCIe3) OK > + .name = "tcsr_pcie_3_clkref_en", > + .offset = 0x54, > + .regulator_names = mahua_tcsr_tx1_rpt012_rx2_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators), > + }, > + [TCSR_PCIE_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { [!] (PCIe6) This needs +RPT2 +RX2 -RX1 > + .name = "tcsr_pcie_4_clkref_en", > + .offset = 0x58, > + .regulator_names = mahua_tcsr_tx1_rpt01_rx1_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), > + }, > + [TCSR_USB2_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (USB_HS) OK > + .name = "tcsr_usb2_1_clkref_en", > + .offset = 0x6c, > + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), > + }, > + [TCSR_USB2_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (MP0_HS) OK > + .name = "tcsr_usb2_2_clkref_en", > + .offset = 0x70, > + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), > + }, > + [TCSR_USB2_3_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (MP1_HS) OK > + .name = "tcsr_usb2_3_clkref_en", > + .offset = 0x74, > + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), > + }, > + [TCSR_USB2_4_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { ("USB2_2") OK> + .name = "tcsr_usb2_4_clkref_en", > + .offset = 0x88, > + .regulator_names = mahua_tcsr_tx1_rpt0_rx0_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators), > + }, > + [TCSR_USB3_0_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (MP0_SS) OK> + .name = "tcsr_usb3_0_clkref_en", > + .offset = 0x64, > + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), > + }, > + [TCSR_USB3_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { (MP1_SS) OK > + .name = "tcsr_usb3_1_clkref_en", > + .offset = 0x68, > + .regulator_names = mahua_tcsr_tx1_rpt345_rx3_regulators, > + .num_regulators = ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), > + }, > + [TCSR_USB4_1_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { OK > + .name = "tcsr_usb4_1_clkref_en", > + .offset = 0x44, > + }, > + [TCSR_USB4_2_CLKREF_EN] = &(const struct qcom_clk_ref_desc) { OK Konrad