From: Jon Hunter <jonathanh@nvidia.com>
To: Mirza Krak <mirza.krak@gmail.com>
Cc: <mark.rutland@arm.com>, Alexandre Courbot <gnurou@gmail.com>,
"Prashant Gaikwad" <pgaikwad@nvidia.com>, <pawel.moll@arm.com>,
Stephen Warren <swarren@wwwdotorg.org>, <pdeschrijver@nvidia.com>,
<ijc+devicetree@hellion.org.uk>, <sboyd@codeaurora.org>,
<linux@armlinux.org.uk>, <robh+dt@kernel.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Kumar Gala <galak@codeaurora.org>, <linux-tegra@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 3/6] dt/bindings: Add bindings for Tegra GMI controller
Date: Wed, 10 Aug 2016 11:13:36 +0100 [thread overview]
Message-ID: <4c8dcec7-0833-af3a-d8c1-106d0ad43007@nvidia.com> (raw)
In-Reply-To: <d72d3f8f-6987-3623-077f-14485679e321@nvidia.com>
On 10/08/16 09:45, Jon Hunter wrote:
>
> On 09/08/16 21:48, Mirza Krak wrote:
>> 2016-08-09 15:34 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>>
>>> On 09/08/16 09:40, Mirza Krak wrote:
>>>> 2016-08-08 16:44 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>>>>
>>>>> On 06/08/16 20:40, Mirza Krak wrote:
>>>>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>>>>
>>
>> <--snip-->
>>
>>>>>> + - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
>>>>>> + Valid values are 0-15, default is 1
>>>>>> + - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
>>>>>> + Valid values are 0-255, default is 1
>>>>>> + - nvidia,snor-wait-width: Number of cycles before READY is asserted.
>>>>>> + Valid values are 0-255, default is 3
>>>>>> +
>>>>>> +Example with two SJA1000 CAN controllers connected to the GMI bus:
>>>>>> +
>>>>>> + gmi@70090000 {
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <1>;
>>>>>
>>>>> I think 0 for size makes sense. I know that caused you problems before,
>>>>> but I am wondering if ...
>>>>>
>>>>>> + ranges;
>>>>>
>>>>> ... ranges is needed here? If we do have it, I am wondering if it should
>>>>> be a single entry for the chip-select that is being used. For now we
>>>>> could only support a ranges with one entry.
>>>>>
>>>>> #address-cells = <1>;
>>>>> #size-cells = <1>;
>>>>> ranges = <4 0x48000000 0x00040000>;
>>>>
>>>> I prefer if we have "ranges" with one single entry, and warn if user enters
>>>> multiple for now, like we discussed earlier. Should have really done it in
>>>> this series.
>>>
>>> I think I do as well.
>>>
>>>>>
>>>>>> + nvidia,snor-mux-mode;
>>>>>> + nvidia,snor-adv-inv;
>>>>>> + nvidia,snor-cs-select = <4>;
>>>>>
>>>>> I would have expected these under bus@X node as they are specific to the
>>>>> GMI CS.
>>>>
>>>> Yes, that is true.
>>>>
>>>>>
>>>>> I would also expect that the actual chip-select number is encoded in the
>>>>> reg property.
>>>>>
>>>>>> +
>>>>>> + bus@0,0 {
>>>>>
>>>>> bus@4
>>>>
>>>> ACK.
>>>>
>>>>>
>>>>> No mention of this bus node in the above documentation.
>>>>
>>>> I was hesitant documenting it since I am not sure if we really need it
>>>> in a generic case? It does make sense in my
>>>> specific case. But what would it look like if we could maintain CS in software.
>>>>
>>>> Do you then have a bus node per CS? I am guessing not. Is it enough to
>>>> document it in my "example brief"?
>>>
>>> I see what you mean. May be it is fine to document with the examples
>>> below how child devices should be populated. You should also state that
>>> currently the GMI only supports one child device currently for the
>>> chip-select that is being used.
>>
>> Should I really need to state that? Is it not always the case, that
>> you have one child device per chip-select?
>
> I think so. Remember it is one child device for the GMI, however, that
> child device could still have one than one child device (per you example
s/one than one/more than one
Jon
--
nvpublic
next prev parent reply other threads:[~2016-08-10 10:13 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-06 19:40 [PATCH 0/6] Add support for Tegra GMI bus controller Mirza Krak
2016-08-06 19:40 ` [PATCH 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Mirza Krak
2016-08-06 19:40 ` [PATCH 2/6] clk: tegra: add TEGRA30_CLK_NOR " Mirza Krak
2016-08-06 19:40 ` [PATCH 3/6] dt/bindings: Add bindings for Tegra GMI controller Mirza Krak
2016-08-08 14:44 ` Jon Hunter
2016-08-09 8:40 ` Mirza Krak
2016-08-09 13:34 ` Jon Hunter
2016-08-09 20:48 ` Mirza Krak
2016-08-10 8:45 ` Jon Hunter
2016-08-10 10:13 ` Jon Hunter [this message]
2016-08-23 10:33 ` Mirza Krak
2016-08-23 14:48 ` Jon Hunter
2016-08-06 19:40 ` [PATCH 4/6] ARM: tegra: Add Tegra30 GMI support Mirza Krak
2016-08-08 15:09 ` Jon Hunter
2016-08-06 19:40 ` [PATCH 5/6] ARM: tegra: Add Tegra20 " Mirza Krak
2016-08-08 15:09 ` Jon Hunter
2016-08-06 19:40 ` [PATCH 6/6] bus: Add support for Tegra Generic Memory Interface Mirza Krak
2016-08-08 13:47 ` Jon Hunter
2016-08-09 7:21 ` Mirza Krak
2016-08-09 13:37 ` Jon Hunter
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