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Thu, 26 Mar 2026 06:39:28 -0700 (PDT) Message-ID: <4d575f17-5cd5-495c-99a9-176b3393d54d@gmail.com> Date: Thu, 26 Mar 2026 14:39:22 +0100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] dt-bindings: Add clock guard DT description To: Krzysztof Kozlowski , Conor Dooley Cc: Rob Herring , Vyacheslav Yurkov , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20260318-feature-clock-guard-v1-0-6137cb4084b7@bruker.com> <20260318-feature-clock-guard-v1-2-6137cb4084b7@bruker.com> <20260318225510.GA639444-robh@kernel.org> <7c7034a7-686a-42c2-bdba-6f31b5179f7c@gmail.com> <20260319-yearly-wrongful-883f7fd86a69@spud> <20260323-sanctuary-semantic-432089feb1c7@spud> <8e7d0c53-aa23-4514-81a5-335a76bb0c45@kernel.org> Content-Language: en-US From: Vyacheslav Yurkov In-Reply-To: <8e7d0c53-aa23-4514-81a5-335a76bb0c45@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 26.03.2026 11:08, Krzysztof Kozlowski wrote: >> >> DTS example: >> clock_guard: clock_controller_guard { >> compatible = "clock-controller-guard"; >> #clock-cells = <1>; >> clocks = <&h2f_clk 0>, <&clk_fgpa_rx 0>, ; >> clock-names = "h2f_clk0", "clk_fpga_rx", "clk_fpga_tx"; >> gpios = <&fpga_ip 0 GPIO_ACTIVE_HIGH>, <&fpga_ip 1 GPIO_ACTIVE_HIGH>; >> gpio-names = "gpio-input0", "gpio-input1"; >> clock-output-names = "clkctrl-guard"; >> }; >> >> custom_device { >> compatible = "..."; >> ... >> #clock-cells = <1>; >> clocks = <&clock_guard 0>; >> clock-names = "clock-guard"; >> }; > > So a pure SW construct? Device has specific clock inputs but you do not > model them and instead replace with one fake-guard-input. > > I don't see how this represents the hardware at all. > > Maybe some diagrams would help, assuming we still talk about hardware. > > Best regards, > Krzysztof Techincally that's correct, it's a software construct. If this is not a right place to submit such a helper driver, I'd appreciate a hint what subsystem is the right one. I was not sure how to provide a diagram in the mailing list, so I posted in on Github https://github.com/OSS-Keepers/clock-controller-guard/issues/1 It is a driver which models dependencies for other drivers. These are soft or "indirect" dependencies, because we cannot access the FPGA unless the FPGA_PLL_locked, and GPIO is telling us we are good to go. Conor, I think this should answer your question as well. Thanks, Slava