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[2a01:c23:bd23:a800:187f:c2cb:1804:1a]) by smtp.googlemail.com with ESMTPSA id gh16-20020a1709073c1000b00711edab7622sm6926593ejc.40.2022.09.06.11.29.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Sep 2022 11:29:19 -0700 (PDT) Message-ID: <52b07db2-7edb-0373-c6d2-df67917f4af7@gmail.com> Date: Tue, 6 Sep 2022 20:29:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.1 Subject: Re: [PATCH RESEND] clk: meson: pll: copy retry workaround from vendor driver Content-Language: en-US To: Jerome Brunet , Yu Tu , Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Jianxin Pan Cc: "open list:ARM/Amlogic Meson..." , linux-clk@vger.kernel.org, "linux-arm-kernel@lists.infradead.org" References: <1jk06rtlrv.fsf@starbuckisacylon.baylibre.com> <09befaaf-b34a-aeda-5dd6-6bfae4b01163@amlogic.com> <1jo7vswmjw.fsf@starbuckisacylon.baylibre.com> From: Heiner Kallweit In-Reply-To: <1jo7vswmjw.fsf@starbuckisacylon.baylibre.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 06.09.2022 17:21, Jerome Brunet wrote: > > On Tue 30 Aug 2022 at 14:33, Yu Tu wrote: > >> On 2022/8/29 17:54, Jerome Brunet wrote: >>> [ EXTERNAL EMAIL ] >>> On Sun 14 Aug 2022 at 23:25, Heiner Kallweit >>> wrote: >>> >>>> On a S905X4-based system this call fails randomly. >>>> The vendor driver has a retry mechanism and on my system >>>> the second attempt is successful always. > > Heiner, ideally commit message should not be about 'your' system > but describe what the system actually is. This would be more useful down > the road. > > Based on Yu Tu feedback I'd propose > > ' > The PCIe PLL locking may be unreliable under some circumstance, such as > high or low temperature. If the PLL fails to lock, reset it a try again. > > This helps on the S905X4 > ' > > If this is OK with you, I can amend the message before applying the > patch, or you may resubmit. As you wish. > Yes, please amend the commit message as suggested. Thanks for the review and follow-up. >>>> >>> This reason looks a bit weak to me. >>> I'd like AML team to comment on this PLL problem as I suspect it might >>> relate to other PLL we have been seeing >> >> First of all, we've had this problem before. But the probability is very >> low, most of the PLL will not lock when the chip is tested at high and low >> temperature. >> >> Our actual code has retry mechanism to solve the above problem. >> >>> >>>> Signed-off-by: Heiner Kallweit >>>> --- >>>> drivers/clk/meson/clk-pll.c | 12 ++++++++---- >>>> 1 file changed, 8 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c >>>> index 9e55617bc..daa025b6d 100644 >>>> --- a/drivers/clk/meson/clk-pll.c >>>> +++ b/drivers/clk/meson/clk-pll.c >>>> @@ -320,12 +320,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) >>>> static int meson_clk_pcie_pll_enable(struct clk_hw *hw) >>>> { >>>> - meson_clk_pll_init(hw); >>>> + int retries = 10; >>>> - if (meson_clk_pll_wait_lock(hw)) >>>> - return -EIO; >>>> + do { >>>> + meson_clk_pll_init(hw); >>>> + if (!meson_clk_pll_wait_lock(hw)) >>>> + return 0; >>>> + pr_info("Retry enabling PCIe PLL clock\n"); >>>> + } while (--retries); >>>> - return 0; >>>> + return -EIO; >>>> } >>>> static int meson_clk_pll_enable(struct clk_hw *hw) >>> . >