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From: Heiko Stuebner <heiko@sntech.de>
To: Lin Huang <hl@rock-chips.com>
Cc: dbasehore@chromium.org, shawn.lin@rock-chips.com,
	briannorris@chromium.org, linux-rockchip@lists.infradead.org,
	dianders@chromium.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399
Date: Fri, 23 Mar 2018 09:26:00 +0100	[thread overview]
Message-ID: <5398945.fsProPGqoW@phil> (raw)
In-Reply-To: <1521511589-17844-1-git-send-email-hl@rock-chips.com>

Am Dienstag, 20. März 2018, 03:06:28 CET schrieb Lin Huang:
> Since hclk_sd and pclk_ddr source clock from CPLL or GPLL,
> and these two PLL may change their frequency. If we do not
> assign right id to pclk_ddr and hclk_sd, they will alway use
> default cur register value, and may get the frequency
> exceed their signed off frequency. So assign correct Id
> for them, then we can assign frequency for them in dts.
> 
> Change-Id: I6c4d15d37ddabe4ed34e2351cf26e660672ae9ee
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

applied for 4.17 after dropping the Change-Id

Thanks
Heiko

      parent reply	other threads:[~2018-03-23  8:26 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-20  2:06 [PATCH v3 1/2] clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 Lin Huang
2018-03-20  2:06 ` [PATCH v3 2/2] arm64: dts: rockchip: assign clock rate for some cpll child clock Lin Huang
2018-03-20  2:12   ` Shawn Lin
2018-03-20  2:23     ` hl
2018-03-20  7:00       ` Heiko Stübner
2018-03-23  8:45   ` Heiko Stuebner
2018-03-23  8:26 ` Heiko Stuebner [this message]

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