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Mon, 28 Sep 2026 01:13:57 -0700 (PDT) X-Received: by 2002:a05:6a00:908c:b0:87e:35ae:783 with SMTP id d2e1a72fcca58-87e9c53ef9fmr10079859b3a.51.1790583236769; Mon, 28 Sep 2026 01:13:56 -0700 (PDT) Received: from [10.218.5.182] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-87feb385ed8sm3799547b3a.45.2026.09.28.01.13.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Sep 2026 01:13:56 -0700 (PDT) Message-ID: <553b2e77-d646-423a-9a80-4d0ae539b919@oss.qualcomm.com> Date: Mon, 28 Sep 2026 13:43:50 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: camcc-nord: Correct camera clock source tables To: Taniya Das , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Konrad Dybcio , Dmitry Baryshkov Cc: Ajit Pandey , Imran Shaik , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260927-fix_camcc-v1-1-9fe956f01f6d@oss.qualcomm.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <20260927-fix_camcc-v1-1-9fe956f01f6d@oss.qualcomm.com> Content-Type: text/plain; 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Use PLL0 main output dividers for the 300 MHz and 400 MHz > CPHY RX rates. > > CSID and IFE Lite use the CPHY RX rates, so share that table rather > than duplicating it. Remove the unsupported 300 MHz CSI PHY timer > rate. > > Fixes: 7647815dfc8f ("clk: qcom: camcc: Add support for camera clock controller for Nord") > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/camcc-nord.c | 22 +++++++--------------- > 1 file changed, 7 insertions(+), 15 deletions(-) > Reviewed-by: Jagadeesh Kona