From: Rhyland Klein <rklein@nvidia.com>
To: Benson Leung <bleung@chromium.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Mike Turquette <mturquette@linaro.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>,
Bill Huang <bilhuang@nvidia.com>,
Paul Walmsley <pwalmsley@nvidia.com>, Jim Lin <jilin@nvidia.com>,
<linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 17/21] clk: tegra: pll: Add logic for SS
Date: Wed, 20 May 2015 13:19:10 -0400 [thread overview]
Message-ID: <555CC20E.8030907@nvidia.com> (raw)
In-Reply-To: <CANLzEks10KmCAx4tK0oSejJ6Z+oBRS2+pcsktvStQrogCarTJQ@mail.gmail.com>
On 5/13/2015 8:25 PM, Benson Leung wrote:
> On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@nvidia.com> wrote:
>> +static void pll_clk_start_ss(struct tegra_clk_pll *pll)
>> +{
>> + if (pll->params->defaults_set && pll->params->ssc_ctrl_en_mask) {
>
> Is there any reason you're checking for the existence of
> ssc_ctrl_en_mask rather than ssc_ctrl_reg?
Not particularly, just a way of seeing if ssc is supported by this pll,
I will change it to check the register to be more consistent with other
checks in the code.
-rhyland
--
nvpublic
next prev parent reply other threads:[~2015-05-20 17:19 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-12 17:23 [PATCH v5 00/21] Tegra210 Clock Support Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 01/21] clk: tegra: Update struct tegra_clk_pll_params kerneldoc Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 01/21] FROMLIST: " Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 02/21] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 03/21] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 04/21] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-05-12 21:52 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 05/21] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 06/21] clk: tegra: pll: update warning msg Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 07/21] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 08/21] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 09/21] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-05-18 22:35 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 10/21] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-05-13 0:01 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 11/21] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-05-12 17:23 ` [PATCH v5 12/21] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-05-13 20:59 ` Benson Leung
2015-05-20 17:24 ` Rhyland Klein
2015-05-20 17:26 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 13/21] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-05-13 22:04 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present Rhyland Klein
2015-05-13 22:11 ` Benson Leung
2015-06-04 18:52 ` Stephen Boyd
2015-05-12 17:23 ` [PATCH v5 15/21] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-05-13 22:20 ` Benson Leung
2015-05-12 17:23 ` [PATCH v5 16/21] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-05-14 0:04 ` Benson Leung
2015-05-20 17:20 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 17/21] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-05-14 0:25 ` Benson Leung
2015-05-20 17:19 ` Rhyland Klein [this message]
2015-05-12 17:24 ` [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-05-14 0:29 ` Benson Leung
2015-05-12 17:24 ` [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-05-13 20:36 ` Benson Leung
2015-05-14 19:37 ` Benson Leung
2015-05-25 8:19 ` Bill Huang
2015-05-12 17:24 ` [PATCH v5 20/21] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-05-14 20:23 ` Benson Leung
2015-05-20 17:17 ` Rhyland Klein
2015-05-20 9:47 ` Jim Lin
2015-05-20 17:16 ` Rhyland Klein
2015-05-12 17:24 ` [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs Rhyland Klein
2015-05-14 20:02 ` Benson Leung
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=555CC20E.8030907@nvidia.com \
--to=rklein@nvidia.com \
--cc=bilhuang@nvidia.com \
--cc=bleung@chromium.org \
--cc=gnurou@gmail.com \
--cc=jilin@nvidia.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mturquette@linaro.org \
--cc=pdeschrijver@nvidia.com \
--cc=pwalmsley@nvidia.com \
--cc=sboyd@codeaurora.org \
--cc=swarren@wwwdotorg.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).