[PATCH 00/11] clk: samsung: exynos7: Cleanup of clock file

[PATCH 00/11] clk: samsung: exynos7: Cleanup of clock file

[Alim Akhtar]

Currently there are lots of ambiguity between clock names in clock file
and in user manual, which leads to lots of confusion for the reviewers.
This series attempts to cleanup the exynos7 clock file as per
user manual naming convention.
This also adds some of the missing Gate clocks which are needed
to complete the clock tree.

First 10 patches are mostly cleanup which does not affect any
functionality to the current code.

Patch 11/11 adds UFS clock addressing review comments [1]
Krzysztof, hope you are ok with including UFS clock patch with this series.

This patch has a dependency on [2]
[1] -> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg46183.html
[2]-> https://www.mail-archive.com/linux-samsung-soc <at> vger.kernel.org/msg46122.html

Alim Akhtar (11):
  clk: samsung: exynos7: Change the CMU_TOPC block clock name
  clk: samsung: exynos7: Corrects CMU_TOP0 clocks names
  clk: samsung: exynos7: Corrects CMU_TOP1 clocks names
  clk: samsung: exynos7: Corrects CMU_CCORE clocks names
  clk: samsung: exynos7: Corrects CMU_PERIC0 clocks names
  clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names
  clk: samsung: exynos7: Corrects CMU_PERIS clocks names
  clk: samsung: exynos7: Corrects CMU_FSYS0 clocks names
  clk: samsung: exynos7: Corrects CMU_FSYS1 clocks names
  clk: samsung: exynos7: Add missing fixed_clks to cmu_info
  clk: samsung: exynos7: Add required clock tree for UFS

 drivers/clk/samsung/clk-exynos7.c       |  430 ++++++++++++++++++++++---------
 include/dt-bindings/clock/exynos7-clk.h |   43 +++-
 2 files changed, 341 insertions(+), 132 deletions(-)

-- 
1.7.10.4

[PATCH 01/11] clk: samsung: exynos7: Change the CMU_TOPC block clock name

[Alim Akhtar]

Corrects the CMU_TOPC block clock name as per user manual.
This also adds few of the missing gate clocks of topc block.
This does not change any functionalies.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   90 +++++++++++++++++++------------
 include/dt-bindings/clock/exynos7-clk.h |   11 +++-
 2 files changed, 67 insertions(+), 34 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 380608b..2394bde 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -35,38 +35,39 @@
 #define DIV_TOPC1		0x0604
 #define DIV_TOPC3		0x060C
 #define ENABLE_ACLK_TOPC1	0x0804
+#define ENABLE_SCLK_TOPC1	0x0A04
 
 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
-	FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
 	FFACTOR(0, "ffac_topc_bus0_pll_div4",
 		"ffac_topc_bus0_pll_div2", 1, 2, 0),
-	FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
-	FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
-	FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
 };
 
 /* List of parent clocks for Muxes in CMU_TOPC */
-PNAME(mout_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
-PNAME(mout_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
-PNAME(mout_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
-PNAME(mout_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
-PNAME(mout_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
+PNAME(mout_topc_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
+PNAME(mout_topc_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
+PNAME(mout_topc_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
+PNAME(mout_topc_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
+PNAME(mout_topc_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
 
-PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
-	"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
-	"mout_sclk_mfc_pll_cmuc" };
+PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
+	"mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
+	"mout_topc_mfc_pll_half" };
 
-PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
+PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
 	"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
-PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
+PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
 	"ffac_topc_bus1_pll_div2"};
-PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
+PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
 	"ffac_topc_cc_pll_div2"};
-PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
+PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
 	"ffac_topc_mfc_pll_div2"};
 
 
-PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
+PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
 	"ffac_topc_bus0_pll_div2"};
 
 static unsigned long topc_clk_regs[] __initdata = {
@@ -90,22 +91,26 @@ static unsigned long topc_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock topc_mux_clks[] __initdata = {
-	MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
-	MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
-	MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
-	MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
-
-	MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
+	MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
+		MUX_SEL_TOPC0, 0, 1),
+	MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
+		MUX_SEL_TOPC0, 4, 1),
+	MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
+		MUX_SEL_TOPC0, 8, 1),
+	MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
+		MUX_SEL_TOPC0, 12, 1),
+	MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
 		MUX_SEL_TOPC0, 16, 2),
-	MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
+	MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
 		MUX_SEL_TOPC0, 20, 1),
-	MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
+	MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
 		MUX_SEL_TOPC0, 24, 1),
-	MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
+	MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
 		MUX_SEL_TOPC0, 28, 1),
 
-	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
-	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
+	MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
+		MUX_SEL_TOPC1, 0, 1),
+	MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
 		MUX_SEL_TOPC1, 16, 1),
 
 	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
@@ -123,15 +128,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
 	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
 		DIV_TOPC1, 24, 4),
 
-	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
+	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
 		DIV_TOPC3, 0, 4),
-	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
+	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
 		DIV_TOPC3, 8, 4),
-	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
+	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
 		DIV_TOPC3, 12, 4),
-	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
+	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
 		DIV_TOPC3, 16, 4),
-	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
+	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
 		DIV_TOPC3, 28, 4),
 };
 
@@ -143,6 +148,25 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
 static struct samsung_gate_clock topc_gate_clks[] __initdata = {
 	GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
 		ENABLE_ACLK_TOPC1, 20, 0, 0),
+
+	GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
+		ENABLE_SCLK_TOPC1, 20, 0, 0),
+	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
+		ENABLE_SCLK_TOPC1, 17, 0, 0),
+	GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
+		ENABLE_SCLK_TOPC1, 16, 0, 0),
+	GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
+		ENABLE_SCLK_TOPC1, 13, 0, 0),
+	GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
+		ENABLE_SCLK_TOPC1, 12, 0, 0),
+	GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
+		ENABLE_SCLK_TOPC1, 5, 0, 0),
+	GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
+		ENABLE_SCLK_TOPC1, 4, 0, 0),
+	GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
+		ENABLE_SCLK_TOPC1, 1, 0, 0),
+	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
+		ENABLE_SCLK_TOPC1, 0, 0, 0),
 };
 
 static struct samsung_pll_clock topc_pll_clks[] __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index e33c75a..b63eba6 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -21,7 +21,16 @@
 #define ACLK_MSCL_532			8
 #define DOUT_SCLK_AUD_PLL		9
 #define FOUT_AUD_PLL			10
-#define TOPC_NR_CLK			11
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define TOPC_NR_CLK			20
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1		1
-- 
1.7.10.4

Re: [PATCH 01/11] clk: samsung: exynos7: Change the CMU_TOPC block clock name

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> Corrects the CMU_TOPC block clock name as per user manual.
> This also adds few of the missing gate clocks of topc block.
> This does not change any functionalies.

s/functionalies/functionalities/

Yes, it does change. After adding new gates without users, kernel will
disable them. Previously these gates remained in default reset state
(probably "pass") or in state set by bootloader (also "pass").

Please update the changelog and of course test the patchset for any
issues in different components depending on these clocks. Depending
directly or indirectly.

Split the patch into:
1. clean up/rename,
2. addition of new mux/gate clock.

Currently it is more difficult to review the patch.

Best regards,
Krzysztof


> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |   90 +++++++++++++++++++------------
>  include/dt-bindings/clock/exynos7-clk.h |   11 +++-
>  2 files changed, 67 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index 380608b..2394bde 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -35,38 +35,39 @@
>  #define DIV_TOPC1		0x0604
>  #define DIV_TOPC3		0x060C
>  #define ENABLE_ACLK_TOPC1	0x0804
> +#define ENABLE_SCLK_TOPC1	0x0A04
>  
>  static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
> -	FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
> +	FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
>  	FFACTOR(0, "ffac_topc_bus0_pll_div4",
>  		"ffac_topc_bus0_pll_div2", 1, 2, 0),
> -	FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
> -	FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
> -	FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
> +	FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
> +	FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
> +	FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
>  };
>  
>  /* List of parent clocks for Muxes in CMU_TOPC */
> -PNAME(mout_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
> -PNAME(mout_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
> -PNAME(mout_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
> -PNAME(mout_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
> -PNAME(mout_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
> +PNAME(mout_topc_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
> +PNAME(mout_topc_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
> +PNAME(mout_topc_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
> +PNAME(mout_topc_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
> +PNAME(mout_topc_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
>  
> -PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
> -	"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
> -	"mout_sclk_mfc_pll_cmuc" };
> +PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
> +	"mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
> +	"mout_topc_mfc_pll_half" };
>  
> -PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
> +PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
>  	"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
> -PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
> +PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
>  	"ffac_topc_bus1_pll_div2"};
> -PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
> +PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
>  	"ffac_topc_cc_pll_div2"};
> -PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
> +PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
>  	"ffac_topc_mfc_pll_div2"};
>  
>  
> -PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
> +PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
>  	"ffac_topc_bus0_pll_div2"};
>  
>  static unsigned long topc_clk_regs[] __initdata = {
> @@ -90,22 +91,26 @@ static unsigned long topc_clk_regs[] __initdata = {
>  };
>  
>  static struct samsung_mux_clock topc_mux_clks[] __initdata = {
> -	MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
> -	MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
> -	MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
> -	MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
> -
> -	MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
> +	MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
> +		MUX_SEL_TOPC0, 0, 1),
> +	MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
> +		MUX_SEL_TOPC0, 4, 1),
> +	MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
> +		MUX_SEL_TOPC0, 8, 1),
> +	MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
> +		MUX_SEL_TOPC0, 12, 1),
> +	MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
>  		MUX_SEL_TOPC0, 16, 2),
> -	MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
> +	MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
>  		MUX_SEL_TOPC0, 20, 1),
> -	MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
> +	MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
>  		MUX_SEL_TOPC0, 24, 1),
> -	MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
> +	MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
>  		MUX_SEL_TOPC0, 28, 1),
>  
> -	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
> -	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
> +	MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
> +		MUX_SEL_TOPC1, 0, 1),
> +	MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
>  		MUX_SEL_TOPC1, 16, 1),
>  
>  	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
> @@ -123,15 +128,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
>  	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
>  		DIV_TOPC1, 24, 4),
>  
> -	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
> +	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
>  		DIV_TOPC3, 0, 4),
> -	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
> +	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
>  		DIV_TOPC3, 8, 4),
> -	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
> +	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
>  		DIV_TOPC3, 12, 4),
> -	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
> +	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
>  		DIV_TOPC3, 16, 4),
> -	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
> +	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
>  		DIV_TOPC3, 28, 4),
>  };
>  
> @@ -143,6 +148,25 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
>  static struct samsung_gate_clock topc_gate_clks[] __initdata = {
>  	GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
>  		ENABLE_ACLK_TOPC1, 20, 0, 0),
> +
> +	GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
> +		ENABLE_SCLK_TOPC1, 20, 0, 0),
> +	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
> +		ENABLE_SCLK_TOPC1, 17, 0, 0),
> +	GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
> +		ENABLE_SCLK_TOPC1, 16, 0, 0),
> +	GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
> +		ENABLE_SCLK_TOPC1, 13, 0, 0),
> +	GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
> +		ENABLE_SCLK_TOPC1, 12, 0, 0),
> +	GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
> +		ENABLE_SCLK_TOPC1, 5, 0, 0),
> +	GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
> +		ENABLE_SCLK_TOPC1, 4, 0, 0),
> +	GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
> +		ENABLE_SCLK_TOPC1, 1, 0, 0),
> +	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
> +		ENABLE_SCLK_TOPC1, 0, 0, 0),
>  };
>  
>  static struct samsung_pll_clock topc_pll_clks[] __initdata = {
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index e33c75a..b63eba6 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -21,7 +21,16 @@
>  #define ACLK_MSCL_532			8
>  #define DOUT_SCLK_AUD_PLL		9
>  #define FOUT_AUD_PLL			10
> -#define TOPC_NR_CLK			11
> +#define SCLK_AUD_PLL			11
> +#define SCLK_MFC_PLL_B			12
> +#define SCLK_MFC_PLL_A			13
> +#define SCLK_BUS1_PLL_B			14
> +#define SCLK_BUS1_PLL_A			15
> +#define SCLK_BUS0_PLL_B			16
> +#define SCLK_BUS0_PLL_A			17
> +#define SCLK_CC_PLL_B			18
> +#define SCLK_CC_PLL_A			19
> +#define TOPC_NR_CLK			20
>  
>  /* TOP0 */
>  #define DOUT_ACLK_PERIC1		1
> 

Re: [PATCH 01/11] clk: samsung: exynos7: Change the CMU_TOPC block clock name

[Alim Akhtar]

Hi Krzysztof,

On 09/07/2015 11:03 AM, Krzysztof Kozlowski wrote:
> On 04.09.2015 20:37, Alim Akhtar wrote:
>> Corrects the CMU_TOPC block clock name as per user manual.
>> This also adds few of the missing gate clocks of topc block.
>> This does not change any functionalies.
>
> s/functionalies/functionalities/
>
> Yes, it does change. After adding new gates without users, kernel will
> disable them. Previously these gates remained in default reset state
> (probably "pass") or in state set by bootloader (also "pass").
>
My bad, was not enough clear of that, what I mean is these changes does 
not affect the working of the related IPs, yes it does change the status 
of gate clocks.
Will update the commit log.

> Please update the changelog and of course test the patchset for any
> issues in different components depending on these clocks. Depending
> directly or indirectly.
>
> Split the patch into:
> 1. clean up/rename,
> 2. addition of new mux/gate clock.
>
This patch adds few of the gate clocks, the reason I added it here 
because subsequent patches in this series can use it.
Or may I should move these new addition to the patch 02/11, as 02/11 is 
going to use them.
Do you think that make sense to you?

> Currently it is more difficult to review the patch.
>
Thanks for your time, do you have any comments of the other patches in 
this series?

> Best regards,
> Krzysztof
>
>
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos7.c       |   90 +++++++++++++++++++------------
>>   include/dt-bindings/clock/exynos7-clk.h |   11 +++-
>>   2 files changed, 67 insertions(+), 34 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index 380608b..2394bde 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -35,38 +35,39 @@
>>   #define DIV_TOPC1		0x0604
>>   #define DIV_TOPC3		0x060C
>>   #define ENABLE_ACLK_TOPC1	0x0804
>> +#define ENABLE_SCLK_TOPC1	0x0A04
>>
>>   static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
>> -	FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
>> +	FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
>>   	FFACTOR(0, "ffac_topc_bus0_pll_div4",
>>   		"ffac_topc_bus0_pll_div2", 1, 2, 0),
>> -	FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
>> -	FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
>> -	FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
>> +	FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
>> +	FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
>> +	FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
>>   };
>>
>>   /* List of parent clocks for Muxes in CMU_TOPC */
>> -PNAME(mout_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
>> -PNAME(mout_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
>> -PNAME(mout_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
>> -PNAME(mout_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
>> -PNAME(mout_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
>> +PNAME(mout_topc_aud_pll_ctrl_p)	= { "fin_pll", "fout_aud_pll" };
>> +PNAME(mout_topc_bus0_pll_ctrl_p)	= { "fin_pll", "fout_bus0_pll" };
>> +PNAME(mout_topc_bus1_pll_ctrl_p)	= { "fin_pll", "fout_bus1_pll" };
>> +PNAME(mout_topc_cc_pll_ctrl_p)	= { "fin_pll", "fout_cc_pll" };
>> +PNAME(mout_topc_mfc_pll_ctrl_p)	= { "fin_pll", "fout_mfc_pll" };
>>
>> -PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
>> -	"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
>> -	"mout_sclk_mfc_pll_cmuc" };
>> +PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
>> +	"mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
>> +	"mout_topc_mfc_pll_half" };
>>
>> -PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
>> +PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
>>   	"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
>> -PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
>> +PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
>>   	"ffac_topc_bus1_pll_div2"};
>> -PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
>> +PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
>>   	"ffac_topc_cc_pll_div2"};
>> -PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
>> +PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
>>   	"ffac_topc_mfc_pll_div2"};
>>
>>
>> -PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
>> +PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
>>   	"ffac_topc_bus0_pll_div2"};
>>
>>   static unsigned long topc_clk_regs[] __initdata = {
>> @@ -90,22 +91,26 @@ static unsigned long topc_clk_regs[] __initdata = {
>>   };
>>
>>   static struct samsung_mux_clock topc_mux_clks[] __initdata = {
>> -	MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
>> -	MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
>> -	MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
>> -	MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
>> -
>> -	MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
>> +	MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
>> +		MUX_SEL_TOPC0, 0, 1),
>> +	MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
>> +		MUX_SEL_TOPC0, 4, 1),
>> +	MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
>> +		MUX_SEL_TOPC0, 8, 1),
>> +	MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
>> +		MUX_SEL_TOPC0, 12, 1),
>> +	MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
>>   		MUX_SEL_TOPC0, 16, 2),
>> -	MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
>> +	MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
>>   		MUX_SEL_TOPC0, 20, 1),
>> -	MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
>> +	MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
>>   		MUX_SEL_TOPC0, 24, 1),
>> -	MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
>> +	MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
>>   		MUX_SEL_TOPC0, 28, 1),
>>
>> -	MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
>> -	MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
>> +	MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
>> +		MUX_SEL_TOPC1, 0, 1),
>> +	MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
>>   		MUX_SEL_TOPC1, 16, 1),
>>
>>   	MUX(0, "mout_aclk_ccore_133", mout_topc_group2,	MUX_SEL_TOPC2, 4, 2),
>> @@ -123,15 +128,15 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
>>   	DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
>>   		DIV_TOPC1, 24, 4),
>>
>> -	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
>> +	DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
>>   		DIV_TOPC3, 0, 4),
>> -	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
>> +	DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
>>   		DIV_TOPC3, 8, 4),
>> -	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
>> +	DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
>>   		DIV_TOPC3, 12, 4),
>> -	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
>> +	DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
>>   		DIV_TOPC3, 16, 4),
>> -	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
>> +	DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
>>   		DIV_TOPC3, 28, 4),
>>   };
>>
>> @@ -143,6 +148,25 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
>>   static struct samsung_gate_clock topc_gate_clks[] __initdata = {
>>   	GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
>>   		ENABLE_ACLK_TOPC1, 20, 0, 0),
>> +
>> +	GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
>> +		ENABLE_SCLK_TOPC1, 20, 0, 0),
>> +	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
>> +		ENABLE_SCLK_TOPC1, 17, 0, 0),
>> +	GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
>> +		ENABLE_SCLK_TOPC1, 16, 0, 0),
>> +	GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
>> +		ENABLE_SCLK_TOPC1, 13, 0, 0),
>> +	GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
>> +		ENABLE_SCLK_TOPC1, 12, 0, 0),
>> +	GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
>> +		ENABLE_SCLK_TOPC1, 5, 0, 0),
>> +	GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
>> +		ENABLE_SCLK_TOPC1, 4, 0, 0),
>> +	GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
>> +		ENABLE_SCLK_TOPC1, 1, 0, 0),
>> +	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
>> +		ENABLE_SCLK_TOPC1, 0, 0, 0),
>>   };
>>
>>   static struct samsung_pll_clock topc_pll_clks[] __initdata = {
>> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
>> index e33c75a..b63eba6 100644
>> --- a/include/dt-bindings/clock/exynos7-clk.h
>> +++ b/include/dt-bindings/clock/exynos7-clk.h
>> @@ -21,7 +21,16 @@
>>   #define ACLK_MSCL_532			8
>>   #define DOUT_SCLK_AUD_PLL		9
>>   #define FOUT_AUD_PLL			10
>> -#define TOPC_NR_CLK			11
>> +#define SCLK_AUD_PLL			11
>> +#define SCLK_MFC_PLL_B			12
>> +#define SCLK_MFC_PLL_A			13
>> +#define SCLK_BUS1_PLL_B			14
>> +#define SCLK_BUS1_PLL_A			15
>> +#define SCLK_BUS0_PLL_B			16
>> +#define SCLK_BUS0_PLL_A			17
>> +#define SCLK_CC_PLL_B			18
>> +#define SCLK_CC_PLL_A			19
>> +#define TOPC_NR_CLK			20
>>
>>   /* TOP0 */
>>   #define DOUT_ACLK_PERIC1		1
>>
>
>

Re: [PATCH 01/11] clk: samsung: exynos7: Change the CMU_TOPC block clock name

[Krzysztof Kozlowski]

On 07.09.2015 16:26, Alim Akhtar wrote:
> Hi Krzysztof,
> 
> On 09/07/2015 11:03 AM, Krzysztof Kozlowski wrote:
>> On 04.09.2015 20:37, Alim Akhtar wrote:
>>> Corrects the CMU_TOPC block clock name as per user manual.
>>> This also adds few of the missing gate clocks of topc block.
>>> This does not change any functionalies.
>>
>> s/functionalies/functionalities/
>>
>> Yes, it does change. After adding new gates without users, kernel will
>> disable them. Previously these gates remained in default reset state
>> (probably "pass") or in state set by bootloader (also "pass").
>>
> My bad, was not enough clear of that, what I mean is these changes does
> not affect the working of the related IPs, yes it does change the status
> of gate clocks.
> Will update the commit log.
> 
>> Please update the changelog and of course test the patchset for any
>> issues in different components depending on these clocks. Depending
>> directly or indirectly.
>>
>> Split the patch into:
>> 1. clean up/rename,
>> 2. addition of new mux/gate clock.
>>
> This patch adds few of the gate clocks, the reason I added it here
> because subsequent patches in this series can use it.
> Or may I should move these new addition to the patch 02/11, as 02/11 is
> going to use them.
> Do you think that make sense to you?

>From the reviewer point of view I would prefer to separate renaming from
addition. You can rename the CMU_TOPC in patch #1, add new gates in #2
and continue with the work (more renames).

> 
>> Currently it is more difficult to review the patch.
>>
> Thanks for your time, do you have any comments of the other patches in
> this series?

Not yet. I'll look at them in few days. So it's up to you if you want to
send next version now or wait for my further comments.

Best regards,
Krzysztof

[PATCH 02/11] clk: samsung: exynos7: Corrects CMU_TOP0 clocks names

[Alim Akhtar]

This patch rename CMU_TOP0 clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |   67 ++++++++++++++++++++-----------------
 1 file changed, 37 insertions(+), 30 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 2394bde..f9aac4a 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -225,30 +225,30 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
 #define ENABLE_SCLK_TOP0_PERIC3		0x0A3C
 
 /* List of parent clocks for Muxes in CMU_TOP0 */
-PNAME(mout_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
-PNAME(mout_bus1_pll_p)	= { "fin_pll", "dout_sclk_bus1_pll" };
-PNAME(mout_cc_pll_p)	= { "fin_pll", "dout_sclk_cc_pll" };
-PNAME(mout_mfc_pll_p)	= { "fin_pll", "dout_sclk_mfc_pll" };
-PNAME(mout_aud_pll_p)	= { "fin_pll", "dout_sclk_aud_pll" };
+PNAME(mout_top0_bus0_pll_user_p)	= { "fin_pll", "sclk_bus0_pll_a" };
+PNAME(mout_top0_bus1_pll_user_p)	= { "fin_pll", "sclk_bus1_pll_a" };
+PNAME(mout_top0_cc_pll_user_p)	= { "fin_pll", "sclk_cc_pll_a" };
+PNAME(mout_top0_mfc_pll_user_p)	= { "fin_pll", "sclk_mfc_pll_a" };
+PNAME(mout_top0_aud_pll_user_p)	= { "fin_pll", "sclk_aud_pll" };
 
-PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
+PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
 	"ffac_top0_bus0_pll_div2"};
-PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
+PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
 	"ffac_top0_bus1_pll_div2"};
-PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
+PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
 	"ffac_top0_cc_pll_div2"};
-PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
+PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
 	"ffac_top0_mfc_pll_div2"};
 
-PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
-	"mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
-	"mout_top0_half_mfc_pll"};
+PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
+	"mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
+	"mout_top0_mfc_pll_half"};
 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
 	"ioclk_audiocdclk1", "ioclk_spdif_extclk",
-	"mout_top0_aud_pll", "mout_top0_half_bus0_pll",
-	"mout_top0_half_bus1_pll"};
-PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
-	"mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
+	"mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
+	"mout_top0_bus1_pll_half"};
+PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
+	"mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
 
 static unsigned long top0_clk_regs[] __initdata = {
 	MUX_SEL_TOP00,
@@ -270,19 +270,24 @@ static unsigned long top0_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock top0_mux_clks[] __initdata = {
-	MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
-	MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
-	MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
-	MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
-	MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
-
-	MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
+	MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
+		MUX_SEL_TOP00, 0, 1),
+	MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
+		MUX_SEL_TOP00, 4, 1),
+	MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
+		MUX_SEL_TOP00, 8, 1),
+	MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
+		MUX_SEL_TOP00, 12, 1),
+	MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
+		MUX_SEL_TOP00, 16, 1),
+
+	MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
 		MUX_SEL_TOP01, 4, 1),
-	MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
+	MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
 		MUX_SEL_TOP01, 8, 1),
-	MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
+	MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
 		MUX_SEL_TOP01, 12, 1),
-	MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
+	MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
 		MUX_SEL_TOP01, 16, 1),
 
 	MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
@@ -357,10 +362,12 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
 };
 
 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
-	FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
-	FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
-	FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
-	FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
+		1, 2, 0),
+	FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
+		1, 2, 0),
+	FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
+	FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
 };
 
 static struct samsung_cmu_info top0_cmu_info __initdata = {
-- 
1.7.10.4

Re: [PATCH 02/11] clk: samsung: exynos7: Corrects CMU_TOP0 clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_TOP0 clocks names to match with user manual.
s/rename/renames/

I did not check the exact renames but overall the patch makes sense and
looks good.

Best regards,
Krzysztof

> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c |   67 ++++++++++++++++++++-----------------
>  1 file changed, 37 insertions(+), 30 deletions(-)
> 

[PATCH 03/11] clk: samsung: exynos7: Corrects CMU_TOP1 clocks names

[Alim Akhtar]

This patch rename CMU_TOP1 clocks names to match with user manual.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |   50 ++++++++++++++++++++-----------------
 1 file changed, 27 insertions(+), 23 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index f9aac4a..ba84e9b 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -409,23 +409,23 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
 #define ENABLE_SCLK_TOP1_FSYS11		0x0A2C
 
 /* List of parent clocks for Muxes in CMU_TOP1 */
-PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
-PNAME(mout_top1_bus1_pll_p)	= { "fin_pll", "dout_sclk_bus1_pll_b" };
-PNAME(mout_top1_cc_pll_p)	= { "fin_pll", "dout_sclk_cc_pll_b" };
-PNAME(mout_top1_mfc_pll_p)	= { "fin_pll", "dout_sclk_mfc_pll_b" };
+PNAME(mout_top1_bus0_pll_user_p)	= { "fin_pll", "sclk_bus0_pll_b" };
+PNAME(mout_top1_bus1_pll_user_p)	= { "fin_pll", "sclk_bus1_pll_b" };
+PNAME(mout_top1_cc_pll_user_p)	= { "fin_pll", "sclk_cc_pll_b" };
+PNAME(mout_top1_mfc_pll_user_p)	= { "fin_pll", "sclk_mfc_pll_b" };
 
-PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
+PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
 	"ffac_top1_bus0_pll_div2"};
-PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
+PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
 	"ffac_top1_bus1_pll_div2"};
-PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
+PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
 	"ffac_top1_cc_pll_div2"};
-PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
+PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
 	"ffac_top1_mfc_pll_div2"};
 
-PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
-	"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
-	"mout_top1_half_mfc_pll"};
+PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
+	"mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
+	"mout_top1_mfc_pll_half"};
 
 static unsigned long top1_clk_regs[] __initdata = {
 	MUX_SEL_TOP10,
@@ -445,20 +445,22 @@ static unsigned long top1_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock top1_mux_clks[] __initdata = {
-	MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
-	MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
-	MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
+	MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
+		MUX_SEL_TOP10, 4, 1),
+	MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
+		MUX_SEL_TOP10, 8, 1),
+	MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
 		MUX_SEL_TOP10, 12, 1),
-	MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
+	MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
 		MUX_SEL_TOP10, 16, 1),
 
-	MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
+	MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
 		MUX_SEL_TOP11, 4, 1),
-	MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
+	MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
 		MUX_SEL_TOP11, 8, 1),
-	MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
+	MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
 		MUX_SEL_TOP11, 12, 1),
-	MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
+	MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
 		MUX_SEL_TOP11, 16, 1),
 
 	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
@@ -502,10 +504,12 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 };
 
 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
-	FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
-	FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
-	FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
-	FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
+		1, 2, 0),
+	FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
+		1, 2, 0),
+	FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
+	FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
 };
 
 static struct samsung_cmu_info top1_cmu_info __initdata = {
-- 
1.7.10.4

[PATCH 04/11] clk: samsung: exynos7: Corrects CMU_CCORE clocks names

[Alim Akhtar]

This patch rename CMU_CCROE clocks names to match with user manual.
And also adds missing gate clock for aclk_ccore_133.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |    8 ++++++--
 include/dt-bindings/clock/exynos7-clk.h |    3 ++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index ba84e9b..0eb0f57 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -31,6 +31,7 @@
 #define MUX_SEL_TOPC1		0x0204
 #define MUX_SEL_TOPC2		0x0208
 #define MUX_SEL_TOPC3		0x020C
+#define MUX_ENABLE_TOPC2	0x0308
 #define DIV_TOPC0		0x0600
 #define DIV_TOPC1		0x0604
 #define DIV_TOPC3		0x060C
@@ -167,6 +168,9 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
 		ENABLE_SCLK_TOPC1, 1, 0, 0),
 	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
 		ENABLE_SCLK_TOPC1, 0, 0, 0),
+
+	GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
+		MUX_ENABLE_TOPC2, 4, 0, 0),
 };
 
 static struct samsung_pll_clock topc_pll_clks[] __initdata = {
@@ -544,7 +548,7 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
 /*
  * List of parent clocks for Muxes in CMU_CCORE
  */
-PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "dout_aclk_ccore_133" };
+PNAME(mout_aclk_ccore_133_user_p)	= { "fin_pll", "aclk_ccore_133" };
 
 static unsigned long ccore_clk_regs[] __initdata = {
 	MUX_SEL_CCORE,
@@ -552,7 +556,7 @@ static unsigned long ccore_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
-	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
+	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
 		MUX_SEL_CCORE, 1, 1),
 };
 
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index b63eba6..2e01235 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -30,7 +30,8 @@
 #define SCLK_BUS0_PLL_A			17
 #define SCLK_CC_PLL_B			18
 #define SCLK_CC_PLL_A			19
-#define TOPC_NR_CLK			20
+#define ACLK_CCORE_133			20
+#define TOPC_NR_CLK			21
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1		1
-- 
1.7.10.4

Re: [PATCH 04/11] clk: samsung: exynos7: Corrects CMU_CCORE clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_CCROE clocks names to match with user manual.

s/rename/renames/ (everywhere...)
s/CCROE/CCORE/


> And also adds missing gate clock for aclk_ccore_133.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |    8 ++++++--
>  include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index ba84e9b..0eb0f57 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -31,6 +31,7 @@
>  #define MUX_SEL_TOPC1		0x0204
>  #define MUX_SEL_TOPC2		0x0208
>  #define MUX_SEL_TOPC3		0x020C
> +#define MUX_ENABLE_TOPC2	0x0308
>  #define DIV_TOPC0		0x0600
>  #define DIV_TOPC1		0x0604
>  #define DIV_TOPC3		0x060C
> @@ -167,6 +168,9 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
>  		ENABLE_SCLK_TOPC1, 1, 0, 0),
>  	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
>  		ENABLE_SCLK_TOPC1, 0, 0, 0),
> +
> +	GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
> +		MUX_ENABLE_TOPC2, 4, 0, 0),

Hmmm... Shouldn't this be CLK_ENABLE_ACLK_TOPC0 register? For other
similar clock configurations (e.g. SCLK_I2S1) the gate at the end is
controlled, not the mux parent.

Best regards,
Krzysztof

>  };
>  
>  static struct samsung_pll_clock topc_pll_clks[] __initdata = {
> @@ -544,7 +548,7 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
>  /*
>   * List of parent clocks for Muxes in CMU_CCORE
>   */
> -PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "dout_aclk_ccore_133" };
> +PNAME(mout_aclk_ccore_133_user_p)	= { "fin_pll", "aclk_ccore_133" };
>  
>  static unsigned long ccore_clk_regs[] __initdata = {
>  	MUX_SEL_CCORE,
> @@ -552,7 +556,7 @@ static unsigned long ccore_clk_regs[] __initdata = {
>  };
>  
>  static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
> -	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
> +	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
>  		MUX_SEL_CCORE, 1, 1),
>  };
>  
> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
> index b63eba6..2e01235 100644
> --- a/include/dt-bindings/clock/exynos7-clk.h
> +++ b/include/dt-bindings/clock/exynos7-clk.h
> @@ -30,7 +30,8 @@
>  #define SCLK_BUS0_PLL_A			17
>  #define SCLK_CC_PLL_B			18
>  #define SCLK_CC_PLL_A			19
> -#define TOPC_NR_CLK			20
> +#define ACLK_CCORE_133			20
> +#define TOPC_NR_CLK			21
>  
>  /* TOP0 */
>  #define DOUT_ACLK_PERIC1		1
> 

Re: [PATCH 04/11] clk: samsung: exynos7: Corrects CMU_CCORE clocks names

[Alim Akhtar]

Hello,

On 09/08/2015 01:00 PM, Krzysztof Kozlowski wrote:
> On 04.09.2015 20:37, Alim Akhtar wrote:
>> This patch rename CMU_CCROE clocks names to match with user manual.
>
> s/rename/renames/ (everywhere...)
> s/CCROE/CCORE/
>
>
>> And also adds missing gate clock for aclk_ccore_133.
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos7.c       |    8 ++++++--
>>   include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>>   2 files changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
>> index ba84e9b..0eb0f57 100644
>> --- a/drivers/clk/samsung/clk-exynos7.c
>> +++ b/drivers/clk/samsung/clk-exynos7.c
>> @@ -31,6 +31,7 @@
>>   #define MUX_SEL_TOPC1		0x0204
>>   #define MUX_SEL_TOPC2		0x0208
>>   #define MUX_SEL_TOPC3		0x020C
>> +#define MUX_ENABLE_TOPC2	0x0308
>>   #define DIV_TOPC0		0x0600
>>   #define DIV_TOPC1		0x0604
>>   #define DIV_TOPC3		0x060C
>> @@ -167,6 +168,9 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
>>   		ENABLE_SCLK_TOPC1, 1, 0, 0),
>>   	GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
>>   		ENABLE_SCLK_TOPC1, 0, 0, 0),
>> +
>> +	GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
>> +		MUX_ENABLE_TOPC2, 4, 0, 0),
>
> Hmmm... Shouldn't this be CLK_ENABLE_ACLK_TOPC0 register? For other
> similar clock configurations (e.g. SCLK_I2S1) the gate at the end is
> controlled, not the mux parent.
Good catch, will re-spin, as suggested by you, will separate adding Gate 
and renaming clock names.
>
> Best regards,
> Krzysztof
>
>>   };
>>
>>   static struct samsung_pll_clock topc_pll_clks[] __initdata = {
>> @@ -544,7 +548,7 @@ CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
>>   /*
>>    * List of parent clocks for Muxes in CMU_CCORE
>>    */
>> -PNAME(mout_aclk_ccore_133_p)	= { "fin_pll", "dout_aclk_ccore_133" };
>> +PNAME(mout_aclk_ccore_133_user_p)	= { "fin_pll", "aclk_ccore_133" };
>>
>>   static unsigned long ccore_clk_regs[] __initdata = {
>>   	MUX_SEL_CCORE,
>> @@ -552,7 +556,7 @@ static unsigned long ccore_clk_regs[] __initdata = {
>>   };
>>
>>   static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
>> -	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
>> +	MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
>>   		MUX_SEL_CCORE, 1, 1),
>>   };
>>
>> diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
>> index b63eba6..2e01235 100644
>> --- a/include/dt-bindings/clock/exynos7-clk.h
>> +++ b/include/dt-bindings/clock/exynos7-clk.h
>> @@ -30,7 +30,8 @@
>>   #define SCLK_BUS0_PLL_A			17
>>   #define SCLK_CC_PLL_B			18
>>   #define SCLK_CC_PLL_A			19
>> -#define TOPC_NR_CLK			20
>> +#define ACLK_CCORE_133			20
>> +#define TOPC_NR_CLK			21
>>
>>   /* TOP0 */
>>   #define DOUT_ACLK_PERIC1		1
>>
>
>

[PATCH 05/11] clk: samsung: exynos7: Corrects CMU_PERIC0 clocks names

[Alim Akhtar]

This patch rename CMU_PERIC0 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric0_66.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   12 ++++++++----
 include/dt-bindings/clock/exynos7-clk.h |    3 ++-
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 0eb0f57..782943b 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -223,6 +223,7 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
 #define DIV_TOP0_PERIC1			0x0634
 #define DIV_TOP0_PERIC2			0x0638
 #define DIV_TOP0_PERIC3			0x063C
+#define ENABLE_ACLK_TOP03		0x080C
 #define ENABLE_SCLK_TOP0_PERIC0		0x0A30
 #define ENABLE_SCLK_TOP0_PERIC1		0x0A34
 #define ENABLE_SCLK_TOP0_PERIC2		0x0A38
@@ -337,6 +338,9 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
 };
 
 static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+	GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
+		ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
+
 	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
 		ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
@@ -589,8 +593,8 @@ CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
 #define ENABLE_SCLK_PERIC0		0x0A00
 
 /* List of parent clocks for Muxes in CMU_PERIC0 */
-PNAME(mout_aclk_peric0_66_p)	= { "fin_pll", "dout_aclk_peric0_66" };
-PNAME(mout_sclk_uart0_p)	= { "fin_pll", "sclk_uart0" };
+PNAME(mout_aclk_peric0_66_user_p)	= { "fin_pll", "aclk_peric0_66" };
+PNAME(mout_sclk_uart0_user_p)	= { "fin_pll", "sclk_uart0" };
 
 static unsigned long peric0_clk_regs[] __initdata = {
 	MUX_SEL_PERIC0,
@@ -599,9 +603,9 @@ static unsigned long peric0_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
-	MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
+	MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
 		MUX_SEL_PERIC0, 0, 1),
-	MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
+	MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
 		MUX_SEL_PERIC0, 16, 1),
 };
 
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 2e01235..ba60a20 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -48,7 +48,8 @@
 #define CLK_SCLK_SPDIF			12
 #define CLK_SCLK_PCM1			13
 #define CLK_SCLK_I2S1			14
-#define TOP0_NR_CLK			15
+#define CLK_ACLK_PERIC0_66		15
+#define TOP0_NR_CLK			16
 
 /* TOP1 */
 #define DOUT_ACLK_FSYS1_200		1
-- 
1.7.10.4

Re: [PATCH 05/11] clk: samsung: exynos7: Corrects CMU_PERIC0 clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_PERIC0 clocks names to match with user manual.
> And also adds missing gate clock for aclk_peric0_66.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |   12 ++++++++----
>  include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>  2 files changed, 10 insertions(+), 5 deletions(-)
> 

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

[PATCH 06/11] clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names

[Alim Akhtar]

This patch rename CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   38 ++++++++++++++++---------------
 include/dt-bindings/clock/exynos7-clk.h |    3 ++-
 2 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 782943b..696489a 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -340,6 +340,8 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
 static struct samsung_gate_clock top0_gate_clks[] __initdata = {
 	GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
 		ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
+		ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
 
 	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
 		ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
@@ -662,15 +664,15 @@ CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
 	exynos7_clk_peric0_init);
 
 /* List of parent clocks for Muxes in CMU_PERIC1 */
-PNAME(mout_aclk_peric1_66_p)	= { "fin_pll", "dout_aclk_peric1_66" };
-PNAME(mout_sclk_uart1_p)	= { "fin_pll", "sclk_uart1" };
-PNAME(mout_sclk_uart2_p)	= { "fin_pll", "sclk_uart2" };
-PNAME(mout_sclk_uart3_p)	= { "fin_pll", "sclk_uart3" };
-PNAME(mout_sclk_spi0_p)		= { "fin_pll", "sclk_spi0" };
-PNAME(mout_sclk_spi1_p)		= { "fin_pll", "sclk_spi1" };
-PNAME(mout_sclk_spi2_p)		= { "fin_pll", "sclk_spi2" };
-PNAME(mout_sclk_spi3_p)		= { "fin_pll", "sclk_spi3" };
-PNAME(mout_sclk_spi4_p)		= { "fin_pll", "sclk_spi4" };
+PNAME(mout_aclk_peric1_66_user_p)	= { "fin_pll", "aclk_peric1_66" };
+PNAME(mout_sclk_uart1_user_p)	= { "fin_pll", "sclk_uart1" };
+PNAME(mout_sclk_uart2_user_p)	= { "fin_pll", "sclk_uart2" };
+PNAME(mout_sclk_uart3_user_p)	= { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_user_p)		= { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_user_p)		= { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_user_p)		= { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_user_p)		= { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_user_p)		= { "fin_pll", "sclk_spi4" };
 
 static unsigned long peric1_clk_regs[] __initdata = {
 	MUX_SEL_PERIC10,
@@ -681,24 +683,24 @@ static unsigned long peric1_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
-	MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
+	MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
 		MUX_SEL_PERIC10, 0, 1),
 
-	MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
+	MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
 		MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
-	MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
+	MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
 		MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
-	MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
+	MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
 		MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
-	MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
+	MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
 		MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
-	MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
+	MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
 		MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
-	MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
+	MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
 		MUX_SEL_PERIC11, 20, 1),
-	MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
+	MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
 		MUX_SEL_PERIC11, 24, 1),
-	MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
+	MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
 		MUX_SEL_PERIC11, 28, 1),
 };
 
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index ba60a20..5a157f7 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -49,7 +49,8 @@
 #define CLK_SCLK_PCM1			13
 #define CLK_SCLK_I2S1			14
 #define CLK_ACLK_PERIC0_66		15
-#define TOP0_NR_CLK			16
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
 
 /* TOP1 */
 #define DOUT_ACLK_FSYS1_200		1
-- 
1.7.10.4

Re: [PATCH 06/11] clk: samsung: exynos7: Corrects CMU_PERIC1 clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_PERIC1 clocks names to match with user manual.
> And also adds missing gate clock for aclk_peric1_66.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |   38 ++++++++++++++++---------------
>  include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>  2 files changed, 22 insertions(+), 19 deletions(-)

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

[PATCH 07/11] clk: samsung: exynos7: Corrects CMU_PERIS clocks names

[Alim Akhtar]

This patch rename CMU_PERIS clocks names to match with user manual.
And also adds missing gate clock for aclk_peris_66.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |    7 +++++--
 include/dt-bindings/clock/exynos7-clk.h |    3 ++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 696489a..75db751 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -150,6 +150,9 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
 	GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
 		ENABLE_ACLK_TOPC1, 20, 0, 0),
 
+	GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
+		ENABLE_ACLK_TOPC1, 24, 0, 0),
+
 	GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
 		ENABLE_SCLK_TOPC1, 20, 0, 0),
 	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
@@ -788,7 +791,7 @@ CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
 #define ENABLE_SCLK_PERIS_SECURE_CHIPID	0x0A10
 
 /* List of parent clocks for Muxes in CMU_PERIS */
-PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
+PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
 
 static unsigned long peris_clk_regs[] __initdata = {
 	MUX_SEL_PERIS,
@@ -800,7 +803,7 @@ static unsigned long peris_clk_regs[] __initdata = {
 
 static struct samsung_mux_clock peris_mux_clks[] __initdata = {
 	MUX(0, "mout_aclk_peris_66_user",
-		mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
+		mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
 };
 
 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 5a157f7..2876654 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -31,7 +31,8 @@
 #define SCLK_CC_PLL_B			18
 #define SCLK_CC_PLL_A			19
 #define ACLK_CCORE_133			20
-#define TOPC_NR_CLK			21
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1		1
-- 
1.7.10.4

Re: [PATCH 07/11] clk: samsung: exynos7: Corrects CMU_PERIS clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_PERIS clocks names to match with user manual.
> And also adds missing gate clock for aclk_peris_66.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |    7 +++++--
>  include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>  2 files changed, 7 insertions(+), 3 deletions(-)

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

[PATCH 08/11] clk: samsung: exynos7: Corrects CMU_FSYS0 clocks names

[Alim Akhtar]

This patch rename CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   24 ++++++++++++++----------
 include/dt-bindings/clock/exynos7-clk.h |    3 ++-
 2 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 75db751..011685e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -514,6 +514,9 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 		ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
 		ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
+		ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
@@ -851,13 +854,13 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 /*
  * List of parent clocks for Muxes in CMU_FSYS0
  */
-PNAME(mout_aclk_fsys0_200_p)	= { "fin_pll", "dout_aclk_fsys0_200" };
-PNAME(mout_sclk_mmc2_p)		= { "fin_pll", "sclk_mmc2" };
+PNAME(mout_aclk_fsys0_200_user_p)	= { "fin_pll", "aclk_fsys0_200" };
+PNAME(mout_sclk_mmc2_user_p)		= { "fin_pll", "sclk_mmc2" };
 
-PNAME(mout_sclk_usbdrd300_p)	= { "fin_pll", "sclk_usbdrd300" };
-PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p)	= { "fin_pll",
+PNAME(mout_sclk_usbdrd300_user_p)	= { "fin_pll", "sclk_usbdrd300" };
+PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p)	= { "fin_pll",
 				"phyclk_usbdrd300_udrd30_phyclock" };
-PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p)	= { "fin_pll",
+PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p)	= { "fin_pll",
 				"phyclk_usbdrd300_udrd30_pipe_pclk" };
 
 /* fixed rate clocks used in the FSYS0 block */
@@ -880,18 +883,19 @@ static unsigned long fsys0_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
-	MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
+	MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
 		MUX_SEL_FSYS00, 24, 1),
 
-	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
-	MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
+	MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
+		MUX_SEL_FSYS01, 24, 1),
+	MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
 		MUX_SEL_FSYS01, 28, 1),
 
 	MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
-		mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
+		mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
 		MUX_SEL_FSYS02, 24, 1),
 	MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
-		mout_phyclk_usbdrd300_udrd30_phyclk_p,
+		mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
 		MUX_SEL_FSYS02, 28, 1),
 };
 
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 2876654..667faed 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -62,7 +62,8 @@
 #define CLK_SCLK_MMC2			6
 #define CLK_SCLK_MMC1			7
 #define CLK_SCLK_MMC0			8
-#define TOP1_NR_CLK			9
+#define CLK_ACLK_FSYS0_200		9
+#define TOP1_NR_CLK			10
 
 /* CCORE */
 #define PCLK_RTC			1
-- 
1.7.10.4

Re: [PATCH 08/11] clk: samsung: exynos7: Corrects CMU_FSYS0 clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_FSYS0 clocks names to match with user manual.
> And also adds missing gate clock for aclk_fsys0_200.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |   24 ++++++++++++++----------
>  include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>  2 files changed, 16 insertions(+), 11 deletions(-)
> 

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

[PATCH 09/11] clk: samsung: exynos7: Corrects CMU_FSYS1 clocks names

[Alim Akhtar]

This patch rename CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |   16 ++++++++++------
 include/dt-bindings/clock/exynos7-clk.h |    3 ++-
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 011685e..f47a2d4 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -517,6 +517,8 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 
 	GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
 		ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
+		ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
@@ -959,9 +961,9 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
 /*
  * List of parent clocks for Muxes in CMU_FSYS1
  */
-PNAME(mout_aclk_fsys1_200_p)	= { "fin_pll",  "dout_aclk_fsys1_200" };
-PNAME(mout_sclk_mmc0_p)		= { "fin_pll", "sclk_mmc0" };
-PNAME(mout_sclk_mmc1_p)		= { "fin_pll", "sclk_mmc1" };
+PNAME(mout_aclk_fsys1_200_user_p)	= { "fin_pll", "aclk_fsys1_200" };
+PNAME(mout_sclk_mmc0_user_p)		= { "fin_pll", "sclk_mmc0" };
+PNAME(mout_sclk_mmc1_user_p)		= { "fin_pll", "sclk_mmc1" };
 
 static unsigned long fsys1_clk_regs[] __initdata = {
 	MUX_SEL_FSYS10,
@@ -970,11 +972,13 @@ static unsigned long fsys1_clk_regs[] __initdata = {
 };
 
 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
-	MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
+	MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
 		MUX_SEL_FSYS10, 28, 1),
 
-	MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
-	MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
+	MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
+		MUX_SEL_FSYS11, 24, 1),
+	MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
+		MUX_SEL_FSYS11, 28, 1),
 };
 
 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 667faed..acdf2e5 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -63,7 +63,8 @@
 #define CLK_SCLK_MMC1			7
 #define CLK_SCLK_MMC0			8
 #define CLK_ACLK_FSYS0_200		9
-#define TOP1_NR_CLK			10
+#define CLK_ACLK_FSYS1_200		10
+#define TOP1_NR_CLK			11
 
 /* CCORE */
 #define PCLK_RTC			1
-- 
1.7.10.4

Re: [PATCH 09/11] clk: samsung: exynos7: Corrects CMU_FSYS1 clocks names

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> This patch rename CMU_FSYS1 clocks names to match with user manual.
> And also adds missing gate clock for aclk_fsys1_200.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |   16 ++++++++++------
>  include/dt-bindings/clock/exynos7-clk.h |    3 ++-
>  2 files changed, 12 insertions(+), 7 deletions(-)

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

[PATCH 10/11] clk: samsung: exynos7: Add missing fixed_clks to cmu_info

[Alim Akhtar]

FSYS0 fixed clocks are not added to fsys0_cmu_info, this make
some of the usb clocks as orphan. This fixes the same.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index f47a2d4..43cfee0 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -936,6 +936,8 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
 };
 
 static struct samsung_cmu_info fsys0_cmu_info __initdata = {
+	.fixed_clks		= fixed_rate_clks_fsys0,
+	.nr_fixed_clks		= ARRAY_SIZE(fixed_rate_clks_fsys0),
 	.mux_clks		= fsys0_mux_clks,
 	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
 	.gate_clks		= fsys0_gate_clks,
-- 
1.7.10.4

Re: [PATCH 10/11] clk: samsung: exynos7: Add missing fixed_clks to cmu_info

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> FSYS0 fixed clocks are not added to fsys0_cmu_info, this make
> some of the usb clocks as orphan. This fixes the same.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c |    2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

[PATCH 11/11] clk: samsung: exynos7: Add required clock tree for UFS

[Alim Akhtar]

Adding required mux/div/gate clocks for UFS controller
present on Exynos7.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/clk/samsung/clk-exynos7.c       |  116 +++++++++++++++++++++++++++++++
 include/dt-bindings/clock/exynos7-clk.h |   24 ++++++-
 2 files changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 43cfee0..ec009be 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -153,6 +153,15 @@ static struct samsung_gate_clock topc_gate_clks[] __initdata = {
 	GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
 		ENABLE_ACLK_TOPC1, 24, 0, 0),
 
+	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
+		ENABLE_SCLK_TOPC1, 17, 0, 0),
+	GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
+		ENABLE_SCLK_TOPC1, 16, 0, 0),
+	GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
+		ENABLE_SCLK_TOPC1, 13, 0, 0),
+	GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
+		ENABLE_SCLK_TOPC1, 12, 0, 0),
+
 	GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
 		ENABLE_SCLK_TOPC1, 20, 0, 0),
 	GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
@@ -479,12 +488,21 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
 	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
 	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
 
+	MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
+		MUX_SEL_TOP1_FSYS0, 0, 2),
 	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
 	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
 		MUX_SEL_TOP1_FSYS0, 28, 2),
 
+	MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
+		MUX_SEL_TOP1_FSYS1, 0, 2),
+	MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
+		MUX_SEL_TOP1_FSYS1, 16, 2),
+
 	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
 	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
+	MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
+		MUX_SEL_TOP1_FSYS11, 24, 2),
 };
 
 static struct samsung_div_clock top1_div_clks[] __initdata = {
@@ -493,6 +511,13 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 	DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
 		DIV_TOP13, 28, 4),
 
+	DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
+		"mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
+
+	DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
+		"mout_sclk_ufsunipro20",
+		DIV_TOP1_FSYS1, 16, 6),
+
 	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
 		DIV_TOP1_FSYS0, 16, 10),
 	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
@@ -502,6 +527,9 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 		DIV_TOP1_FSYS11, 0, 10),
 	DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
 		DIV_TOP1_FSYS11, 12, 10),
+
+	DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
+		"mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
 };
 
 static struct samsung_gate_clock top1_gate_clks[] __initdata = {
@@ -510,6 +538,12 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 	GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
 		ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
 
+	GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
+		ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
+		ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
+
 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
 		ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
@@ -519,6 +553,10 @@ static struct samsung_gate_clock top1_gate_clks[] __initdata = {
 		ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
 		ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
+
+	GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
+		"dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
+		24, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
@@ -958,22 +996,54 @@ CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
 #define MUX_SEL_FSYS10			0x0200
 #define MUX_SEL_FSYS11			0x0204
+#define MUX_SEL_FSYS12			0x0208
+#define DIV_FSYS1			0x0600
 #define ENABLE_ACLK_FSYS1		0x0800
+#define ENABLE_PCLK_FSYS1               0x0900
+#define ENABLE_SCLK_FSYS11              0x0A04
+#define ENABLE_SCLK_FSYS12              0x0A08
+#define ENABLE_SCLK_FSYS13              0x0A0C
 
 /*
  * List of parent clocks for Muxes in CMU_FSYS1
  */
 PNAME(mout_aclk_fsys1_200_user_p)	= { "fin_pll", "aclk_fsys1_200" };
+PNAME(mout_fsys1_group_p)	= { "fin_pll", "fin_pll_26m",
+				"sclk_phy_fsys1_26m" };
 PNAME(mout_sclk_mmc0_user_p)		= { "fin_pll", "sclk_mmc0" };
 PNAME(mout_sclk_mmc1_user_p)		= { "fin_pll", "sclk_mmc1" };
+PNAME(mout_sclk_ufsunipro20_user_p)  = { "fin_pll", "sclk_ufsunipro20" };
+PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
+PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
+PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
+
+/* fixed rate clocks used in the FSYS1 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initdata = {
+	FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
+			CLK_IS_ROOT, 300000000),
+	FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
+			CLK_IS_ROOT, 300000000),
+	FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
+			CLK_IS_ROOT, 300000000),
+};
 
 static unsigned long fsys1_clk_regs[] __initdata = {
 	MUX_SEL_FSYS10,
 	MUX_SEL_FSYS11,
+	MUX_SEL_FSYS12,
+	DIV_FSYS1,
 	ENABLE_ACLK_FSYS1,
+	ENABLE_PCLK_FSYS1,
+	ENABLE_SCLK_FSYS11,
+	ENABLE_SCLK_FSYS12,
+	ENABLE_SCLK_FSYS13,
 };
 
 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
+	MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
+		mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
+	MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
+		 MUX_SEL_FSYS10, 20, 2),
 	MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
 		MUX_SEL_FSYS10, 28, 1),
 
@@ -981,18 +1051,64 @@ static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
 		MUX_SEL_FSYS11, 24, 1),
 	MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
 		MUX_SEL_FSYS11, 28, 1),
+	MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
+		MUX_SEL_FSYS11, 20, 1),
+
+	MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
+		mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
+	MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
+		mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
+	MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
+		mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
+};
+
+static struct samsung_div_clock fsys1_div_clks[] __initdata = {
+	DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
+		DIV_FSYS1, 0, 2),
 };
 
 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
+	GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
+		"mout_sclk_ufsunipro20_user",
+		ENABLE_SCLK_FSYS11, 20, 0, 0),
+
 	GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
 		ENABLE_ACLK_FSYS1, 29, 0, 0),
 	GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
 		ENABLE_ACLK_FSYS1, 30, 0, 0),
+
+	GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
+		ENABLE_ACLK_FSYS1, 31, 0, 0),
+	GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
+		ENABLE_PCLK_FSYS1, 30, 0, 0),
+
+	GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
+		"mout_phyclk_ufs20_rx1_symbol_user",
+		ENABLE_SCLK_FSYS12, 16, 0, 0),
+	GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
+		"mout_phyclk_ufs20_rx0_symbol_user",
+		ENABLE_SCLK_FSYS12, 24, 0, 0),
+	GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
+		"mout_phyclk_ufs20_tx0_symbol_user",
+		ENABLE_SCLK_FSYS12, 28, 0, 0),
+
+	GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
+		"oscclk_phy_clkout_embedded_combo_phy",
+		"fin_pll",
+		ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
+
+	GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
+		"mout_fsys1_phyclk_sel1",
+		ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
 };
 
 static struct samsung_cmu_info fsys1_cmu_info __initdata = {
+	.fixed_clks		= fixed_rate_clks_fsys1,
+	.nr_fixed_clks		= ARRAY_SIZE(fixed_rate_clks_fsys1),
 	.mux_clks		= fsys1_mux_clks,
 	.nr_mux_clks		= ARRAY_SIZE(fsys1_mux_clks),
+	.div_clks		= fsys1_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(fsys1_div_clks),
 	.gate_clks		= fsys1_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
 	.nr_clk_ids		= FSYS1_NR_CLK,
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index acdf2e5..10c5586 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -64,7 +64,14 @@
 #define CLK_SCLK_MMC0			8
 #define CLK_ACLK_FSYS0_200		9
 #define CLK_ACLK_FSYS1_200		10
-#define TOP1_NR_CLK			11
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
 
 /* CCORE */
 #define PCLK_RTC			1
@@ -139,7 +146,20 @@
 /* FSYS1 */
 #define ACLK_MMC1			1
 #define ACLK_MMC0			2
-#define FSYS1_NR_CLK			3
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
 
 /* MSCL */
 #define USERMUX_ACLK_MSCL_532		1
-- 
1.7.10.4

Re: [PATCH 11/11] clk: samsung: exynos7: Add required clock tree for UFS

[Krzysztof Kozlowski]

On 04.09.2015 20:37, Alim Akhtar wrote:
> Adding required mux/div/gate clocks for UFS controller
> present on Exynos7.
> 
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos7.c       |  116 +++++++++++++++++++++++++++++++
>  include/dt-bindings/clock/exynos7-clk.h |   24 ++++++-
>  2 files changed, 138 insertions(+), 2 deletions(-)
> 

My previous comments are fixed, rest looks good:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof

Re: [PATCH 11/11] clk: samsung: exynos7: Add required clock tree for UFS

[Alim Akhtar]

Hi Krzysztof,

On 09/10/2015 09:38 AM, Krzysztof Kozlowski wrote:
> On 04.09.2015 20:37, Alim Akhtar wrote:
>> Adding required mux/div/gate clocks for UFS controller
>> present on Exynos7.
>>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>   drivers/clk/samsung/clk-exynos7.c       |  116 +++++++++++++++++++++++++++++++
>>   include/dt-bindings/clock/exynos7-clk.h |   24 ++++++-
>>   2 files changed, 138 insertions(+), 2 deletions(-)
>>
>
> My previous comments are fixed, rest looks good:
>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>
Thanks for your time and review, have re-send V2 of whole series.
Please take a look.
> Best regards,
> Krzysztof
>
>
>