From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <xuejiancheng@hisilicon.com>
Subject: Re: [PATCH v6 1/6] clk: hisilicon: add CRG driver for hi3519 soc
To: Rob Herring <robh@kernel.org>
References: <1453171111-21921-1-git-send-email-xuejiancheng@huawei.com>
 <1453171111-21921-2-git-send-email-xuejiancheng@huawei.com>
 <20160119182317.GA3681@rob-hp-laptop>
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From: xuejiancheng <xuejiancheng@huawei.com>
Message-ID: <569EE62E.3040003@huawei.com>
Date: Wed, 20 Jan 2016 09:43:10 +0800
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In-Reply-To: <20160119182317.GA3681@rob-hp-laptop>
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List-ID: <linux-clk.vger.kernel.org>


On 2016/1/20 2:23, Rob Herring wrote:
> On Tue, Jan 19, 2016 at 10:38:26AM +0800, Jiancheng Xue wrote:
>> The CRG(Clock and Reset Generator) block provides clock
>> and reset signals for other modules in hi3519 soc.
>>
>> Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
>> ---
>>  .../devicetree/bindings/clock/hi3519-crg.txt       |  46 +++++++
> 
> I already acked this. Please add ack's when posting new versions.
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 
Hi Rob,

I see. Thank you very much.

Regards,
Jiancheng

>>  drivers/clk/hisilicon/Kconfig                      |   7 ++
>>  drivers/clk/hisilicon/Makefile                     |   2 +
>>  drivers/clk/hisilicon/clk-hi3519.c                 | 132 +++++++++++++++++++++
>>  drivers/clk/hisilicon/clk.c                        |  23 ++--
>>  drivers/clk/hisilicon/clk.h                        |  14 +--
>>  drivers/clk/hisilicon/reset.c                      | 130 ++++++++++++++++++++
>>  drivers/clk/hisilicon/reset.h                      |  32 +++++
>>  include/dt-bindings/clock/hi3519-clock.h           |  40 +++++++
>>  9 files changed, 411 insertions(+), 15 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/clock/hi3519-crg.txt
>>  create mode 100644 drivers/clk/hisilicon/clk-hi3519.c
>>  create mode 100644 drivers/clk/hisilicon/reset.c
>>  create mode 100644 drivers/clk/hisilicon/reset.h
>>  create mode 100644 include/dt-bindings/clock/hi3519-clock.h
> 
> .
>