[PATCH 1/4] clk: rockchip: fix cpuclk mux bit of big cpu-cluster

[PATCH 1/4] clk: rockchip: fix cpuclk mux bit of big cpu-cluster

[Heiko Stuebner]

Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
I plan to include them into my clk-fixes branch, so posted for reference
and possible objections ;-)

 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 21f3ea9..f6667b8 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
 	.core_reg = RK3368_CLKSEL_CON(0),
 	.div_core_shift = 0,
 	.div_core_mask = 0x1f,
-	.mux_core_shift = 15,
+	.mux_core_shift = 7,
 };
 
 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
-- 
2.6.4

[PATCH 2/4] clk: rockchip: fix rk3368 cpuclk core dividers

[Heiko Stuebner]

Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3368.c | 40 +++++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index f6667b8..3c9733e 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -218,29 +218,29 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
 	}
 
 static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
-	RK3368_CPUCLKB_RATE(1512000000, 2, 6, 6),
-	RK3368_CPUCLKB_RATE(1488000000, 2, 5, 5),
-	RK3368_CPUCLKB_RATE(1416000000, 2, 5, 5),
-	RK3368_CPUCLKB_RATE(1200000000, 2, 4, 4),
-	RK3368_CPUCLKB_RATE(1008000000, 2, 4, 4),
-	RK3368_CPUCLKB_RATE( 816000000, 2, 3, 3),
-	RK3368_CPUCLKB_RATE( 696000000, 2, 3, 3),
-	RK3368_CPUCLKB_RATE( 600000000, 2, 2, 2),
-	RK3368_CPUCLKB_RATE( 408000000, 2, 2, 2),
-	RK3368_CPUCLKB_RATE( 312000000, 2, 2, 2),
+	RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
+	RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
+	RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
+	RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
+	RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
+	RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
+	RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
+	RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
+	RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
+	RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
 };
 
 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
-	RK3368_CPUCLKL_RATE(1512000000, 2, 7, 7),
-	RK3368_CPUCLKL_RATE(1488000000, 2, 6, 6),
-	RK3368_CPUCLKL_RATE(1416000000, 2, 6, 6),
-	RK3368_CPUCLKL_RATE(1200000000, 2, 5, 5),
-	RK3368_CPUCLKL_RATE(1008000000, 2, 5, 5),
-	RK3368_CPUCLKL_RATE( 816000000, 2, 4, 4),
-	RK3368_CPUCLKL_RATE( 696000000, 2, 3, 3),
-	RK3368_CPUCLKL_RATE( 600000000, 2, 3, 3),
-	RK3368_CPUCLKL_RATE( 408000000, 2, 2, 2),
-	RK3368_CPUCLKL_RATE( 312000000, 2, 2, 2),
+	RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
+	RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
+	RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
+	RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
+	RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
+	RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
+	RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
+	RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
+	RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
+	RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
 };
 
 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
-- 
2.6.4

[PATCH 3/4] clk: rockchip: rk3368: fix parents of video encoder/decoder

[Heiko Stuebner]

The vdpu and vepu clocks can also be parented to the npll and current
parent list also is wrong as it would use the npll as "usbphy" source,
so adapt the parent to the correct one.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3368.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 3c9733e..6037beb 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -384,10 +384,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	 * Clock-Architecture Diagram 3
 	 */
 
-	COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb_p, 0,
+	COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
 			RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3368_CLKGATE_CON(4), 6, GFLAGS),
-	COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb_p, 0,
+	COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
 			RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
 			RK3368_CLKGATE_CON(4), 7, GFLAGS),
 
-- 
2.6.4

[PATCH 4/4] clk: rockchip: rk3368: fix hdmi_cec gate-register

[Heiko Stuebner]

Fix a typo making the sclk_hdmi_cec access a wrong register to handle
its gate.

Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 6037beb..57acb62 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 			RK3368_CLKGATE_CON(4), 13, GFLAGS),
 	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
-			RK3368_CLKGATE_CON(5), 12, GFLAGS),
+			RK3368_CLKGATE_CON(4), 12, GFLAGS),
 
 	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 			RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
-- 
2.6.4

Re: [PATCH 1/4] clk: rockchip: fix cpuclk mux bit of big cpu-cluster

[Stephen Boyd]

On 01/20/2016 01:49 PM, Heiko Stuebner wrote:
> Both clusters have their mux bit in bit 7 of their respective register.
> For whatever reason the big cluster currently lists bit 15 which is
> definitly wrong.
>
> Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
> Reported-by: Zhang Qing <zhangqing@rock-chips.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> I plan to include them into my clk-fixes branch, so posted for reference
> and possible objections ;-)

None of these patches are fixes to regressions introduced in the merge
window for v4.5, so we wouldn't be considering them for clk-fixes. We
can certainly queue them up in clk-next for v4.6 and let stable process
funnel them to the right stable trees though.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 1/4] clk: rockchip: fix cpuclk mux bit of big cpu-cluster

[Heiko Stuebner]

Am Mittwoch, 20. Januar 2016, 14:06:27 schrieb Stephen Boyd:
> On 01/20/2016 01:49 PM, Heiko Stuebner wrote:
> > Both clusters have their mux bit in bit 7 of their respective register.
> > For whatever reason the big cluster currently lists bit 15 which is
> > definitly wrong.
> > 
> > Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
> > Reported-by: Zhang Qing <zhangqing@rock-chips.com>
> > Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> > ---
> > I plan to include them into my clk-fixes branch, so posted for reference
> > and possible objections ;-)
> 
> None of these patches are fixes to regressions introduced in the merge
> window for v4.5, so we wouldn't be considering them for clk-fixes. We
> can certainly queue them up in clk-next for v4.6 and let stable process
> funnel them to the right stable trees though.

ok, I'll move them over to that part then :-)

Re: [PATCH 2/4] clk: rockchip: fix rk3368 cpuclk core dividers

[zhangqing]

hi:

On 01/20/2016 01:49 PM, Heiko Stuebner wrote:
> Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core
> dividers") it seems the cpuclk dividers are one to high on the rk3368
> as well.
>
> And again similar to the previous fix, we opt to make the divider list
> contain the values to be written to use the same paradigm for them on all
> supported socs.
>
> Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
> Reported-by: Zhang Qing <zhangqing@rock-chips.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Reviewed-by: zhangqing <zhangqing@rock-chips.com>

> ---
>   drivers/clk/rockchip/clk-rk3368.c | 40 +++++++++++++++++++--------------------
>   1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
> index f6667b8..3c9733e 100644
> --- a/drivers/clk/rockchip/clk-rk3368.c
> +++ b/drivers/clk/rockchip/clk-rk3368.c
> @@ -218,29 +218,29 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
>   	}
>
>   static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
> -	RK3368_CPUCLKB_RATE(1512000000, 2, 6, 6),
> -	RK3368_CPUCLKB_RATE(1488000000, 2, 5, 5),
> -	RK3368_CPUCLKB_RATE(1416000000, 2, 5, 5),
> -	RK3368_CPUCLKB_RATE(1200000000, 2, 4, 4),
> -	RK3368_CPUCLKB_RATE(1008000000, 2, 4, 4),
> -	RK3368_CPUCLKB_RATE( 816000000, 2, 3, 3),
> -	RK3368_CPUCLKB_RATE( 696000000, 2, 3, 3),
> -	RK3368_CPUCLKB_RATE( 600000000, 2, 2, 2),
> -	RK3368_CPUCLKB_RATE( 408000000, 2, 2, 2),
> -	RK3368_CPUCLKB_RATE( 312000000, 2, 2, 2),
> +	RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
> +	RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
> +	RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
> +	RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
> +	RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
> +	RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
> +	RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
> +	RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
> +	RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
> +	RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
>   };
>
>   static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
> -	RK3368_CPUCLKL_RATE(1512000000, 2, 7, 7),
> -	RK3368_CPUCLKL_RATE(1488000000, 2, 6, 6),
> -	RK3368_CPUCLKL_RATE(1416000000, 2, 6, 6),
> -	RK3368_CPUCLKL_RATE(1200000000, 2, 5, 5),
> -	RK3368_CPUCLKL_RATE(1008000000, 2, 5, 5),
> -	RK3368_CPUCLKL_RATE( 816000000, 2, 4, 4),
> -	RK3368_CPUCLKL_RATE( 696000000, 2, 3, 3),
> -	RK3368_CPUCLKL_RATE( 600000000, 2, 3, 3),
> -	RK3368_CPUCLKL_RATE( 408000000, 2, 2, 2),
> -	RK3368_CPUCLKL_RATE( 312000000, 2, 2, 2),
> +	RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
> +	RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
> +	RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
> +	RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
> +	RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
> +	RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
> +	RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
> +	RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
> +	RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
> +	RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
>   };
>
>   static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
>

Re: [PATCH 3/4] clk: rockchip: rk3368: fix parents of video encoder/decoder

[zhangqing]

hi:

On 01/20/2016 01:49 PM, Heiko Stuebner wrote:
> The vdpu and vepu clocks can also be parented to the npll and current
> parent list also is wrong as it would use the npll as "usbphy" source,
> so adapt the parent to the correct one.
>
> Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Reviewed-by: zhangqing <zhangqing@rock-chips.com>

> ---
>   drivers/clk/rockchip/clk-rk3368.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
> index 3c9733e..6037beb 100644
> --- a/drivers/clk/rockchip/clk-rk3368.c
> +++ b/drivers/clk/rockchip/clk-rk3368.c
> @@ -384,10 +384,10 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
>   	 * Clock-Architecture Diagram 3
>   	 */
>
> -	COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb_p, 0,
> +	COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
>   			RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
>   			RK3368_CLKGATE_CON(4), 6, GFLAGS),
> -	COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb_p, 0,
> +	COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
>   			RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
>   			RK3368_CLKGATE_CON(4), 7, GFLAGS),
>
>

Re: [PATCH 4/4] clk: rockchip: rk3368: fix hdmi_cec gate-register

[zhangqing]

hi:

On 01/20/2016 01:49 PM, Heiko Stuebner wrote:
> Fix a typo making the sclk_hdmi_cec access a wrong register to handle
> its gate.
>
> Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Reviewed-by: zhangqing <zhangqing@rock-chips.com>

> ---
>   drivers/clk/rockchip/clk-rk3368.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
> index 6037beb..57acb62 100644
> --- a/drivers/clk/rockchip/clk-rk3368.c
> +++ b/drivers/clk/rockchip/clk-rk3368.c
> @@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
>   	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
>   			RK3368_CLKGATE_CON(4), 13, GFLAGS),
>   	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
> -			RK3368_CLKGATE_CON(5), 12, GFLAGS),
> +			RK3368_CLKGATE_CON(4), 12, GFLAGS),
>
>   	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
>   			RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
>

Re: [PATCH 1/4] clk: rockchip: fix cpuclk mux bit of big cpu-cluster

[zhangqing]

hi:

On 01/20/2016 01:49 PM, Heiko Stuebner wrote:
> Both clusters have their mux bit in bit 7 of their respective register.
> For whatever reason the big cluster currently lists bit 15 which is
> definitly wrong.
>
> Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
> Reported-by: Zhang Qing <zhangqing@rock-chips.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Reviewed-by: zhangqing <zhangqing@rock-chips.com>

> ---
> I plan to include them into my clk-fixes branch, so posted for reference
> and possible objections ;-)
>
>   drivers/clk/rockchip/clk-rk3368.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
> index 21f3ea9..f6667b8 100644
> --- a/drivers/clk/rockchip/clk-rk3368.c
> +++ b/drivers/clk/rockchip/clk-rk3368.c
> @@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
>   	.core_reg = RK3368_CLKSEL_CON(0),
>   	.div_core_shift = 0,
>   	.div_core_mask = 0x1f,
> -	.mux_core_shift = 15,
> +	.mux_core_shift = 7,
>   };
>
>   static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
>