From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH] clk: tegra210: Add SLCG override gate clocks To: Thierry Reding References: <1457638685-31007-1-git-send-email-rklein@nvidia.com> <20160314160551.GA21898@ulmo.nvidia.com> CC: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Stephen Warren , Alexandre Courbot , Jon Hunter , , , Bill Huang From: Rhyland Klein Message-ID: <56E6E20C.6020807@nvidia.com> Date: Mon, 14 Mar 2016 12:08:44 -0400 MIME-Version: 1.0 In-Reply-To: <20160314160551.GA21898@ulmo.nvidia.com> Content-Type: text/plain; charset="windows-1252" Return-Path: rklein@nvidia.com List-ID: On 3/14/2016 12:05 PM, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Thu, Mar 10, 2016 at 02:38:05PM -0500, Rhyland Klein wrote: >> From: Bill Huang >> >> Add some SLCG (Second Level Clock Gating) override clocks to control >> gating and un-gating their logics. >> >> Signed-off-by: Bill Huang >> Signed-off-by: Rhyland Klein >> --- >> drivers/clk/tegra/clk-id.h | 16 ++++++ >> drivers/clk/tegra/clk-tegra210.c | 91 ++++++++++++++++++++++++++++++++ >> include/dt-bindings/clock/tegra210-car.h | 32 +++++------ >> 3 files changed, 123 insertions(+), 16 deletions(-) > > There's no rationale given here about why we need this. What will these > second level clock gates be used for? Why do we need these (seemingly) > duplicate clock entries. > These are going to be used in the to-be posted patchset around powergating. As of now they are unused, which is why I hadn't added them previously. I just wanted to try to get this dependency in before the powergate series was posted. -rhyland -- nvpublic