From: Richard Weinberger <richard@nod.at>
To: Keguang Zhang <keguang.zhang@gmail.com>,
linux-mips@linux-mips.org, linux-clk@vger.kernel.org,
linux-pm@vger.kernel.org, dmaengine@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-mtd@lists.infradead.org
Cc: Ralf Baechle <ralf@linux-mips.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Vinod Koul <vinod.koul@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Linus Walleij <linus.walleij@linaro.org>,
Alexandre Courbot <gnurou@gmail.com>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>
Subject: Re: [PATCH V2 4/7] mtd: nand: add Loongson1 NAND driver
Date: Fri, 8 Apr 2016 13:52:39 +0200 [thread overview]
Message-ID: <57079B87.9030209@nod.at> (raw)
In-Reply-To: <1460115779-13141-4-git-send-email-keguang.zhang@gmail.com>
Am 08.04.2016 um 13:42 schrieb Keguang Zhang:
> + chip->options = NAND_NO_SUBPAGE_WRITE;
> + chip->ecc.mode = NAND_ECC_SOFT;
Is the lack of HW ECC and subpage write a hardware limitation?
Thanks,
//richard
next prev parent reply other threads:[~2016-04-08 11:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-08 11:42 [PATCH V2 1/7] clk: Loongson1: Update clocks of Loongson1B Keguang Zhang
2016-04-08 11:42 ` [PATCH V2 2/7] cpufreq: Loongson1: Update cpufreq " Keguang Zhang
2016-04-11 3:52 ` Viresh Kumar
2016-04-08 11:42 ` [PATCH V2 3/7] dmaengine: Loongson1: add Loongson1 dmaengine driver Keguang Zhang
2016-04-08 11:42 ` [PATCH V2 4/7] mtd: nand: add Loongson1 NAND driver Keguang Zhang
2016-04-08 11:52 ` Richard Weinberger [this message]
2016-04-08 14:30 ` Kelvin Cheung
2016-04-08 11:42 ` [PATCH V2 6/7] MIPS: Loongson1B: Some updates/fixes for LS1B Keguang Zhang
2016-04-16 9:41 ` [PATCH V2 1/7] clk: Loongson1: Update clocks of Loongson1B Kelvin Cheung
2016-04-18 4:56 ` Stephen Boyd
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