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([2a01:e0a:982:cbb0:760d:c2fa:a66b:fed3]) by smtp.gmail.com with ESMTPSA id p18-20020a05600c359200b0041674bf7d4csm2748727wmq.48.2024.04.10.09.27.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Apr 2024 09:27:47 -0700 (PDT) Message-ID: <57735f4f-aa94-4ca7-8d5b-a95519c5ffd6@linaro.org> Date: Wed, 10 Apr 2024 18:27:46 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 1/4] clk: qcom: dispcc-sm8450: fix DisplayPort clocks To: Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240408-dispcc-dp-clocks-v1-0-f9e44902c28d@linaro.org> <20240408-dispcc-dp-clocks-v1-1-f9e44902c28d@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20240408-dispcc-dp-clocks-v1-1-f9e44902c28d@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 08/04/2024 13:47, Dmitry Baryshkov wrote: > On SM8450 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. > > Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- > 1 file changed, 4 insertions(+), 16 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c > index 92e9c4e7b13d..49bb4f58c391 100644 > --- a/drivers/clk/qcom/dispcc-sm8450.c > +++ b/drivers/clk/qcom/dispcc-sm8450.c > @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { > - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { > .cmd_rcgr = 0x819c, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > Reviewed-by: Neil Armstrong I can't test, but I assume you tested on your HDK8450 Thanks, Neil