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Tue, 19 Dec 2023 04:06:30 -0800 (PST) Received: from [192.168.1.20] ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id rg8-20020a1709076b8800b00a1f7cbf2896sm14306470ejc.176.2023.12.19.04.06.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Dec 2023 04:06:29 -0800 (PST) Message-ID: <58ded02d-a5d2-40e2-b575-dc520a7553cf@linaro.org> Date: Tue, 19 Dec 2023 13:06:25 +0100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] clk: samsung: Fix typo error and extra space To: Varada Pavani , mturquette@baylibre.com, sboyd@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: linux-samsung-soc@vger.kernel.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com References: <20231219115834.65720-1-v.pavani@samsung.com> <20231219115834.65720-2-v.pavani@samsung.com> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 19/12/2023 12:58, Varada Pavani wrote: > Remove extra spaces and fix spelling mistakes in 'drivers/ > clk/samsung/clk-cpu.c' and 'drivers/clk/samsung/clk-cpu.h' > > Signed-off-by: Varada Pavani > --- > drivers/clk/samsung/clk-cpu.c | 6 +++--- > drivers/clk/samsung/clk-cpu.h | 2 +- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c > index 3e62ade120c5..18568b8b1b9b 100644 > --- a/drivers/clk/samsung/clk-cpu.c > +++ b/drivers/clk/samsung/clk-cpu.c > @@ -19,7 +19,7 @@ > * clock and the corresponding rate changes of the auxillary clocks of the CPU > * domain. The platform clock driver provides a clock register configuration > * for each configurable rate which is then used to program the clock hardware > - * registers to acheive a fast co-oridinated rate change for all the CPU domain > + * registers to achieve a fast co-oridinated rate change for all the CPU domain > * clocks. > * > * On a rate change request for the CPU clock, the rate change is propagated > @@ -181,7 +181,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, > * If the old parent clock speed is less than the clock speed of > * the alternate parent, then it should be ensured that at no point > * the armclk speed is more than the old_prate until the dividers are > - * set. Also workaround the issue of the dividers being set to lower > + * set. Also workaround the issue of the dividers being set to lower Why? The double-space is correct. > * values before the parent clock speed is set to new lower speed > * (this can result in too high speed of armclk output clocks). > */ > @@ -303,7 +303,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, > * If the old parent clock speed is less than the clock speed of > * the alternate parent, then it should be ensured that at no point > * the armclk speed is more than the old_prate until the dividers are > - * set. Also workaround the issue of the dividers being set to lower > + * set. Also workaround the issue of the dividers being set to lower Why? > * values before the parent clock speed is set to new lower speed > * (this can result in too high speed of armclk output clocks). > */ > diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h > index fc9f67a3b22e..e0a1651174e6 100644 > --- a/drivers/clk/samsung/clk-cpu.h > +++ b/drivers/clk/samsung/clk-cpu.h > @@ -33,7 +33,7 @@ struct exynos_cpuclk_cfg_data { > * @hw: handle between CCF and CPU clock. > * @alt_parent: alternate parent clock to use when switching the speed > * of the primary parent clock. > - * @ctrl_base: base address of the clock controller. > + * @ctrl_base: base address of the clock controller. Why only here and not in other places? Best regards, Krzysztof