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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id eo6-20020a056512480600b005135b81f30asm2144123lfb.97.2024.03.13.11.36.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Mar 2024 11:36:09 -0700 (PDT) Message-ID: <58f07908-127a-438d-84e2-e059f269859b@linaro.org> Date: Wed, 13 Mar 2024 19:36:06 +0100 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure Content-Language: en-US To: Gabor Juhos , Bjorn Andersson , Michael Turquette , Stephen Boyd , Sricharan Ramabadhran , Dmitry Baryshkov , Gokul Sriram Palanisamy Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20240311-apss-ipq-pll-ipq5018-hang-v1-1-8ed42b7a904d@gmail.com> From: Konrad Dybcio In-Reply-To: <20240311-apss-ipq-pll-ipq5018-hang-v1-1-8ed42b7a904d@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/11/24 16:06, Gabor Juhos wrote: > Booting v6.8 results in a hang on various IPQ5018 based boards. > Investigating the problem showed that the hang happens when the > clk_alpha_pll_stromer_plus_set_rate() function tries to write > into the PLL_MODE register of the APSS PLL. > > Checking the downstream code revealed that it uses [1] stromer > specific operations for IPQ5018, whereas in the current code > the stromer plus specific operations are used. > > The ops in the 'ipq_pll_stromer_plus' clock definition can't be > changed since that is needed for IPQ5332, so add a new alpha pll > clock declaration which uses the correct stromer ops and use this > new clock for IPQ5018 to avoid the boot failure. > > 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c#L67 > > Cc: stable@vger.kernel.org > Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018") > Signed-off-by: Gabor Juhos > --- > Based on v6.8. > --- > drivers/clk/qcom/apss-ipq-pll.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c > index 678b805f13d45..11f1ae59438f7 100644 > --- a/drivers/clk/qcom/apss-ipq-pll.c > +++ b/drivers/clk/qcom/apss-ipq-pll.c > @@ -55,6 +55,24 @@ static struct clk_alpha_pll ipq_pll_huayra = { > }, > }; > > +static struct clk_alpha_pll ipq_pll_stromer = { > + .offset = 0x0, > + .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], CLK_ALPHA_PLL_TYPE_STROMER? [...] > static const struct apss_pll_data ipq5018_pll_data = { > .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, and here? The L register differs, so the rattesetting done from Linux must have never worked anyway? Konrad