* [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks
2017-06-08 14:17 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Sylwester Nawrocki
@ 2017-06-08 14:17 ` Sylwester Nawrocki
2017-06-08 17:05 ` Krzysztof Kozlowski
2017-06-09 2:26 ` Chanwoo Choi
2017-06-08 14:17 ` [PATCH 3/3] clk: samsung: exynos542x: Add EPLL rate table Sylwester Nawrocki
` (2 subsequent siblings)
3 siblings, 2 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2017-06-08 14:17 UTC (permalink / raw)
To: linux-samsung-soc, linux-clk
Cc: cw00.choi, krzk, b.zolnierkie, Sylwester Nawrocki
This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
Changes since RFC version:
- dropped one clean up chunk
---
drivers/clk/samsung/clk-exynos5420.c | 10 +++++++---
include/dt-bindings/clock/exynos5420.h | 3 +++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index cdc092a..6f1d6c0 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -487,6 +487,7 @@ static void __init exynos5420_clk_sleep_init(void) {}
PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
+PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock
@@ -536,8 +537,8 @@ static void __init exynos5420_clk_sleep_init(void) {}
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
- MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
- 20, 2),
+ MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
+ SRC_TOP7, 20, 2),
MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
@@ -546,6 +547,8 @@ static void __init exynos5420_clk_sleep_init(void) {}
MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
+ MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
+ SRC_TOP9, 8, 1),
MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
SRC_TOP9, 16, 1),
MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
@@ -703,7 +706,7 @@ static void __init exynos5420_clk_sleep_init(void) {}
MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
- MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
+ MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
@@ -1399,6 +1402,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
if (_get_rate("fin_pll") == 24 * MHZ) {
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 6fd21c2..2740ae0 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -217,6 +217,9 @@
#define CLK_MOUT_MCLK_CDREX 654
#define CLK_MOUT_BPLL 655
#define CLK_MOUT_MX_MSPLL_CCORE 656
+#define CLK_MOUT_EPLL 657
+#define CLK_MOUT_MAU_EPLL 658
+#define CLK_MOUT_USER_MAU_EPLL 659
/* divider clocks */
#define CLK_DOUT_PIXEL 768
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks
2017-06-08 14:17 ` [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks Sylwester Nawrocki
@ 2017-06-08 17:05 ` Krzysztof Kozlowski
2017-06-09 2:26 ` Chanwoo Choi
1 sibling, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2017-06-08 17:05 UTC (permalink / raw)
To: Sylwester Nawrocki; +Cc: linux-samsung-soc, linux-clk, cw00.choi, b.zolnierkie
On Thu, Jun 08, 2017 at 04:17:12PM +0200, Sylwester Nawrocki wrote:
> This patch adds missing definitions of mux clocks required for using
> EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes since RFC version:
> - dropped one clean up chunk
> ---
> drivers/clk/samsung/clk-exynos5420.c | 10 +++++++---
> include/dt-bindings/clock/exynos5420.h | 3 +++
> 2 files changed, 10 insertions(+), 3 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks
2017-06-08 14:17 ` [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks Sylwester Nawrocki
2017-06-08 17:05 ` Krzysztof Kozlowski
@ 2017-06-09 2:26 ` Chanwoo Choi
1 sibling, 0 replies; 10+ messages in thread
From: Chanwoo Choi @ 2017-06-09 2:26 UTC (permalink / raw)
To: Sylwester Nawrocki, linux-samsung-soc, linux-clk; +Cc: krzk, b.zolnierkie
Hi Sylwester,
Looks good to me. I tested it on Odroid-Xu3 board.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
On 2017년 06월 08일 23:17, Sylwester Nawrocki wrote:
> This patch adds missing definitions of mux clocks required for using
> EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes since RFC version:
> - dropped one clean up chunk
> ---
> drivers/clk/samsung/clk-exynos5420.c | 10 +++++++---
> include/dt-bindings/clock/exynos5420.h | 3 +++
> 2 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index cdc092a..6f1d6c0 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -487,6 +487,7 @@ static void __init exynos5420_clk_sleep_init(void) {}
> PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
> PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
> PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
> +PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
>
> /* fixed rate clocks generated outside the soc */
> static struct samsung_fixed_rate_clock
> @@ -536,8 +537,8 @@ static void __init exynos5420_clk_sleep_init(void) {}
>
> MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
> mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
> - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
> - 20, 2),
> + MUX(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
> + SRC_TOP7, 20, 2),
> MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
> MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
>
> @@ -546,6 +547,8 @@ static void __init exynos5420_clk_sleep_init(void) {}
> MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
> MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
>
> + MUX(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
> + SRC_TOP9, 8, 1),
> MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
> SRC_TOP9, 16, 1),
> MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
> @@ -703,7 +706,7 @@ static void __init exynos5420_clk_sleep_init(void) {}
> MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
> MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
> MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
> - MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
> + MUX(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
> MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
> MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
>
> @@ -1399,6 +1402,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>
> if (_get_rate("fin_pll") == 24 * MHZ) {
> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> + exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> }
> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index 6fd21c2..2740ae0 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -217,6 +217,9 @@
> #define CLK_MOUT_MCLK_CDREX 654
> #define CLK_MOUT_BPLL 655
> #define CLK_MOUT_MX_MSPLL_CCORE 656
> +#define CLK_MOUT_EPLL 657
> +#define CLK_MOUT_MAU_EPLL 658
> +#define CLK_MOUT_USER_MAU_EPLL 659
>
> /* divider clocks */
> #define CLK_DOUT_PIXEL 768
> --
> 1.9.1
>
>
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] clk: samsung: exynos542x: Add EPLL rate table
2017-06-08 14:17 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Sylwester Nawrocki
2017-06-08 14:17 ` [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks Sylwester Nawrocki
@ 2017-06-08 14:17 ` Sylwester Nawrocki
2017-06-09 3:59 ` Chanwoo Choi
2017-06-08 17:04 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Krzysztof Kozlowski
2017-06-09 1:59 ` Chanwoo Choi
3 siblings, 1 reply; 10+ messages in thread
From: Sylwester Nawrocki @ 2017-06-08 14:17 UTC (permalink / raw)
To: linux-samsung-soc, linux-clk
Cc: cw00.choi, krzk, b.zolnierkie, Sylwester Nawrocki
A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as a multiple of various
audio sampling rates.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6f1d6c0..0ba71bf 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1280,2 +1280,2 @@ static void __init exynos5420_clk_sleep_init(void) {}
PLL_35XX_RATE(200000000, 200, 3, 3),
};
+static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
+ PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
+ PLL_36XX_RATE(400000000U, 200, 2, 2, 0),
+ PLL_36XX_RATE(393216000U, 197, 3, 2, 25690),
+ PLL_36XX_RATE(361267200U, 301, 5, 2, 3671),
+ PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
+ PLL_36XX_RATE(196608000U, 197, 3, 3, -25690),
+ PLL_36XX_RATE(180633600U, 301, 5, 3, 3671),
+ PLL_36XX_RATE(131072000U, 131, 3, 3, 4719),
+ PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
+ PLL_36XX_RATE(65536000U, 131, 3, 4, 4719),
+ PLL_36XX_RATE(49152000U, 197, 3, 5, 25690),
+ PLL_36XX_RATE(45158400U, 301, 5, 3, 3671),
+ PLL_36XX_RATE(32768000U, 131, 3, 5, 4719),
+};
+
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL),
@@ -1287,7 +1303,7 @@ static void __init exynos5420_clk_sleep_init(void) {}
CPLL_CON0, NULL),
[dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
DPLL_CON0, NULL),
- [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
+ [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
EPLL_CON0, NULL),
[rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
RPLL_CON0, NULL),
@@ -1402,7 +1418,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
if (_get_rate("fin_pll") == 24 * MHZ) {
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
- exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 3/3] clk: samsung: exynos542x: Add EPLL rate table
2017-06-08 14:17 ` [PATCH 3/3] clk: samsung: exynos542x: Add EPLL rate table Sylwester Nawrocki
@ 2017-06-09 3:59 ` Chanwoo Choi
2017-06-09 10:32 ` Sylwester Nawrocki
0 siblings, 1 reply; 10+ messages in thread
From: Chanwoo Choi @ 2017-06-09 3:59 UTC (permalink / raw)
To: Sylwester Nawrocki, linux-samsung-soc, linux-clk; +Cc: krzk, b.zolnierkie
Hi Sylwester,
On 2017년 06월 08일 23:17, Sylwester Nawrocki wrote:
> A specific clock rate table is added for EPLL so it is possible
> to set frequency of the EPLL output clock as a multiple of various
> audio sampling rates.
>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 6f1d6c0..0ba71bf 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1280,2 +1280,2 @@ static void __init exynos5420_clk_sleep_init(void) {}
> PLL_35XX_RATE(200000000, 200, 3, 3),
> };
>
I got a following frequency(Recalc rate) value.
I think there are two much different value for 400000000U and 45158400U.
fin_pll Recalc rate mdiv pdiv sdiv kdiv
24000000 600000000 100 2 1 0
24000000 400000000 200 3 2 0
24000000 394784008.5 197 3 2 25690
24000000 361267219 301 5 2 3671
24000000 200000000 200 3 3 0
24000000 196607995.7 197 3 3 -25690
24000000 180633609.5 301 5 3 3671
24000000 131072007.3 131 3 3 4719
24000000 100000000 200 3 4 0
24000000 65536003.66 131 3 4 4719
24000000 49348001.07 197 3 5 25690
24000000 180633609.5 301 5 3 3671
24000000 32768001.83 131 3 5 4719
> +static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
> + PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
> + PLL_36XX_RATE(400000000U, 200, 2, 2, 0),
For 400MHz, pdiv is 3 instead of 2 as following:
PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
> + PLL_36XX_RATE(393216000U, 197, 3, 2, 25690),
> + PLL_36XX_RATE(361267200U, 301, 5, 2, 3671),
> + PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
> + PLL_36XX_RATE(196608000U, 197, 3, 3, -25690),
> + PLL_36XX_RATE(180633600U, 301, 5, 3, 3671),
> + PLL_36XX_RATE(131072000U, 131, 3, 3, 4719),
> + PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
> + PLL_36XX_RATE(65536000U, 131, 3, 4, 4719),
> + PLL_36XX_RATE(49152000U, 197, 3, 5, 25690),
> + PLL_36XX_RATE(45158400U, 301, 5, 3, 3671),
I got the fout value (180633609) instead of 45158400U
when I used the M(301) P(5) S(3) K(3671).
fin_pll Recalc rate mdiv pdiv sdiv kdiv
24000000 180633609 301 5 3 3671
> + PLL_36XX_RATE(32768000U, 131, 3, 5, 4719),
> +};
> +
> static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
> [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> APLL_CON0, NULL),
> @@ -1287,7 +1303,7 @@ static void __init exynos5420_clk_sleep_init(void) {}
> CPLL_CON0, NULL),
> [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
> DPLL_CON0, NULL),
> - [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
> + [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
> EPLL_CON0, NULL),
> [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
> RPLL_CON0, NULL),
> @@ -1402,7 +1418,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
>
> if (_get_rate("fin_pll") == 24 * MHZ) {
> exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> - exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> + exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> }
> --
> 1.9.1
>
>
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 3/3] clk: samsung: exynos542x: Add EPLL rate table
2017-06-09 3:59 ` Chanwoo Choi
@ 2017-06-09 10:32 ` Sylwester Nawrocki
0 siblings, 0 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2017-06-09 10:32 UTC (permalink / raw)
To: Chanwoo Choi; +Cc: linux-samsung-soc, linux-clk, krzk, b.zolnierkie
On 06/09/2017 05:59 AM, Chanwoo Choi wrote:
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -1280,2 +1280,2 @@ static void __init exynos5420_clk_sleep_init(void) {}
>> PLL_35XX_RATE(200000000, 200, 3, 3),
>> };
>>
> I got a following frequency(Recalc rate) value.
> I think there are two much different value for 400000000U and 45158400U.
>
> fin_pll Recalc rate mdiv pdiv sdiv kdiv
> 24000000 600000000 100 2 1 0
> 24000000 400000000 200 3 2 0
> 24000000 394784008.5 197 3 2 25690
> 24000000 361267219 301 5 2 3671
> 24000000 200000000 200 3 3 0
> 24000000 196607995.7 197 3 3 -25690
> 24000000 180633609.5 301 5 3 3671
> 24000000 131072007.3 131 3 3 4719
> 24000000 100000000 200 3 4 0
> 24000000 65536003.66 131 3 4 4719
> 24000000 49348001.07 197 3 5 25690
> 24000000 180633609.5 301 5 3 3671
> 24000000 32768001.83 131 3 5 4719
>
>
>> +static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
>> + PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
>> + PLL_36XX_RATE(400000000U, 200, 2, 2, 0),
> For 400MHz, pdiv is 3 instead of 2 as following:
> PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
Thanks a lot for testing this, I originally just verified 131072000U,
180633600U, 196608000U values. I'll amend this entry and will post
v2 of the patch series shortly.
>> + PLL_36XX_RATE(393216000U, 197, 3, 2, 25690),
>> + PLL_36XX_RATE(361267200U, 301, 5, 2, 3671),
>> + PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
>> + PLL_36XX_RATE(196608000U, 197, 3, 3, -25690),
>> + PLL_36XX_RATE(180633600U, 301, 5, 3, 3671),
>> + PLL_36XX_RATE(131072000U, 131, 3, 3, 4719),
>> + PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
>> + PLL_36XX_RATE(65536000U, 131, 3, 4, 4719),
>> + PLL_36XX_RATE(49152000U, 197, 3, 5, 25690),
>> + PLL_36XX_RATE(45158400U, 301, 5, 3, 3671),
>
> I got the fout value (180633609) instead of 45158400U
> when I used the M(301) P(5) S(3) K(3671).
>
> fin_pll Recalc rate mdiv pdiv sdiv kdiv
> 24000000 180633609 301 5 3 3671
I'm going to drop this entry as it is not really needed now.
>> + PLL_36XX_RATE(32768000U, 131, 3, 5, 4719),
>> +};
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks
2017-06-08 14:17 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Sylwester Nawrocki
2017-06-08 14:17 ` [PATCH 2/3] clk: samsung: Add missing exynos5420 audio related clocks Sylwester Nawrocki
2017-06-08 14:17 ` [PATCH 3/3] clk: samsung: exynos542x: Add EPLL rate table Sylwester Nawrocki
@ 2017-06-08 17:04 ` Krzysztof Kozlowski
2017-06-09 10:19 ` Sylwester Nawrocki
2017-06-09 1:59 ` Chanwoo Choi
3 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2017-06-08 17:04 UTC (permalink / raw)
To: Sylwester Nawrocki; +Cc: linux-samsung-soc, linux-clk, cw00.choi, b.zolnierkie
On Thu, Jun 08, 2017 at 04:17:11PM +0200, Sylwester Nawrocki wrote:
> The existing enable/disable ops for PLL35XX are made more generic
> and used also for PLL36XX. This fixes issues in the kernel with
> PLL36XX PLLs when the PLL has not been already enabled by bootloader.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes since RFC version:
> - fixed wrong bit handling in samsung_pll3xxx_disable()
> - pll->lock_offs used and comment improved in samsung_pll35xx_set_rate()
> ---
> drivers/clk/samsung/clk-pll.c | 87 +++++++++++++++++++++++++------------------
> 1 file changed, 50 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 5229089..5c4899c 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -23,6 +23,10 @@ struct samsung_clk_pll {
> struct clk_hw hw;
> void __iomem *lock_reg;
> void __iomem *con_reg;
> + /* PLL enable control bit offset in @con_reg register */
> + unsigned short enable_offs;
> + /* PLL lock status bit offset in @con_reg register */
> + unsigned short lock_offs;
> enum samsung_pll_type type;
> unsigned int rate_count;
> const struct samsung_pll_rate_table *rate_table;
> @@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
> return rate_table[i - 1].rate;
> }
>
> +static int samsung_pll3xxx_enable(struct clk_hw *hw)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 tmp;
> +
> + tmp = readl_relaxed(pll->con_reg);
> + tmp |= BIT(pll->enable_offs);
> + writel_relaxed(tmp, pll->con_reg);
> +
> + /* wait lock time */
> + do {
> + cpu_relax();
> + tmp = readl_relaxed(pll->con_reg);
> + } while (!(tmp & BIT(pll->lock_offs)));
> +
> + return 0;
> +}
> +
> +static void samsung_pll3xxx_disable(struct clk_hw *hw)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 tmp;
> +
> + tmp = readl_relaxed(pll->con_reg);
> + tmp &= ~BIT(pll->enable_offs);
> + writel_relaxed(tmp, pll->con_reg);
> +}
> +
> /*
> * PLL2126 Clock Type
> */
> @@ -142,34 +174,6 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
> #define PLL35XX_LOCK_STAT_SHIFT (29)
> #define PLL35XX_ENABLE_SHIFT (31)
>
> -static int samsung_pll35xx_enable(struct clk_hw *hw)
> -{
> - struct samsung_clk_pll *pll = to_clk_pll(hw);
> - u32 tmp;
> -
> - tmp = readl_relaxed(pll->con_reg);
> - tmp |= BIT(PLL35XX_ENABLE_SHIFT);
> - writel_relaxed(tmp, pll->con_reg);
> -
> - /* wait_lock_time */
> - do {
> - cpu_relax();
> - tmp = readl_relaxed(pll->con_reg);
> - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT)));
> -
> - return 0;
> -}
> -
> -static void samsung_pll35xx_disable(struct clk_hw *hw)
> -{
> - struct samsung_clk_pll *pll = to_clk_pll(hw);
> - u32 tmp;
> -
> - tmp = readl_relaxed(pll->con_reg);
> - tmp &= ~BIT(PLL35XX_ENABLE_SHIFT);
> - writel_relaxed(tmp, pll->con_reg);
> -}
> -
> static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> @@ -238,12 +242,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
> (rate->sdiv << PLL35XX_SDIV_SHIFT);
> writel_relaxed(tmp, pll->con_reg);
>
> - /* wait_lock_time if enabled */
> - if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) {
> + /* Wait until the PLL is locked if it is enabled. */
> + if (tmp & BIT(pll->enable_offs)) {
> do {
> cpu_relax();
> tmp = readl_relaxed(pll->con_reg);
> - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT)));
> + } while (!(tmp & BIT(pll->lock_offs)));
> }
> return 0;
> }
> @@ -252,8 +256,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
> .recalc_rate = samsung_pll35xx_recalc_rate,
> .round_rate = samsung_pll_round_rate,
> .set_rate = samsung_pll35xx_set_rate,
> - .enable = samsung_pll35xx_enable,
> - .disable = samsung_pll35xx_disable,
> + .enable = samsung_pll3xxx_enable,
> + .disable = samsung_pll3xxx_disable,
> };
>
> static const struct clk_ops samsung_pll35xx_clk_min_ops = {
> @@ -275,6 +279,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
> #define PLL36XX_SDIV_SHIFT (0)
> #define PLL36XX_KDIV_SHIFT (0)
> #define PLL36XX_LOCK_STAT_SHIFT (29)
> +#define PLL36XX_ENABLE_SHIFT (31)
Everything looks good... but you are aware that lock_stat and enable
offsets are equal to PLL35XX so thedisable/enable ops could be re-used
directly?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks
2017-06-08 17:04 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Krzysztof Kozlowski
@ 2017-06-09 10:19 ` Sylwester Nawrocki
0 siblings, 0 replies; 10+ messages in thread
From: Sylwester Nawrocki @ 2017-06-09 10:19 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: linux-samsung-soc, linux-clk, cw00.choi, b.zolnierkie
On 06/08/2017 07:04 PM, Krzysztof Kozlowski wrote:
> Everything looks good... but you are aware that lock_stat and enable
> offsets are equal to PLL35XX so the disable/enable ops could be re-used
> directly?
I planned to add enable/disable ops for all PLLs and there are different
bit offsets used for some PLLs than 29 and 31, e.g. PLL2650XX.
I just reworked the $subject patch to reuse the pll35xx callback functions
for pll36xx but I think it's better to leave this patch as is, so it is
easier to handle differences across the PLLs.
--
Thanks,
Sylwester
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks
2017-06-08 14:17 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Sylwester Nawrocki
` (2 preceding siblings ...)
2017-06-08 17:04 ` [PATCH 1/3] clk: samsung: Add enable/disable operation for PLL36XX clocks Krzysztof Kozlowski
@ 2017-06-09 1:59 ` Chanwoo Choi
3 siblings, 0 replies; 10+ messages in thread
From: Chanwoo Choi @ 2017-06-09 1:59 UTC (permalink / raw)
To: Sylwester Nawrocki, linux-samsung-soc, linux-clk; +Cc: krzk, b.zolnierkie
Hi Sylwester,
Looks good to me. I tested it on Exynos325-based Rinato board
which uses the PLL36xx/PLL35xx.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
On 2017년 06월 08일 23:17, Sylwester Nawrocki wrote:
> The existing enable/disable ops for PLL35XX are made more generic
> and used also for PLL36XX. This fixes issues in the kernel with
> PLL36XX PLLs when the PLL has not been already enabled by bootloader.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes since RFC version:
> - fixed wrong bit handling in samsung_pll3xxx_disable()
> - pll->lock_offs used and comment improved in samsung_pll35xx_set_rate()
> ---
> drivers/clk/samsung/clk-pll.c | 87 +++++++++++++++++++++++++------------------
> 1 file changed, 50 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 5229089..5c4899c 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -23,6 +23,10 @@ struct samsung_clk_pll {
> struct clk_hw hw;
> void __iomem *lock_reg;
> void __iomem *con_reg;
> + /* PLL enable control bit offset in @con_reg register */
> + unsigned short enable_offs;
> + /* PLL lock status bit offset in @con_reg register */
> + unsigned short lock_offs;
> enum samsung_pll_type type;
> unsigned int rate_count;
> const struct samsung_pll_rate_table *rate_table;
> @@ -61,6 +65,34 @@ static long samsung_pll_round_rate(struct clk_hw *hw,
> return rate_table[i - 1].rate;
> }
>
> +static int samsung_pll3xxx_enable(struct clk_hw *hw)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 tmp;
> +
> + tmp = readl_relaxed(pll->con_reg);
> + tmp |= BIT(pll->enable_offs);
> + writel_relaxed(tmp, pll->con_reg);
> +
> + /* wait lock time */
> + do {
> + cpu_relax();
> + tmp = readl_relaxed(pll->con_reg);
> + } while (!(tmp & BIT(pll->lock_offs)));
> +
> + return 0;
> +}
> +
> +static void samsung_pll3xxx_disable(struct clk_hw *hw)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 tmp;
> +
> + tmp = readl_relaxed(pll->con_reg);
> + tmp &= ~BIT(pll->enable_offs);
> + writel_relaxed(tmp, pll->con_reg);
> +}
> +
> /*
> * PLL2126 Clock Type
> */
> @@ -142,34 +174,6 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw,
> #define PLL35XX_LOCK_STAT_SHIFT (29)
> #define PLL35XX_ENABLE_SHIFT (31)
>
> -static int samsung_pll35xx_enable(struct clk_hw *hw)
> -{
> - struct samsung_clk_pll *pll = to_clk_pll(hw);
> - u32 tmp;
> -
> - tmp = readl_relaxed(pll->con_reg);
> - tmp |= BIT(PLL35XX_ENABLE_SHIFT);
> - writel_relaxed(tmp, pll->con_reg);
> -
> - /* wait_lock_time */
> - do {
> - cpu_relax();
> - tmp = readl_relaxed(pll->con_reg);
> - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT)));
> -
> - return 0;
> -}
> -
> -static void samsung_pll35xx_disable(struct clk_hw *hw)
> -{
> - struct samsung_clk_pll *pll = to_clk_pll(hw);
> - u32 tmp;
> -
> - tmp = readl_relaxed(pll->con_reg);
> - tmp &= ~BIT(PLL35XX_ENABLE_SHIFT);
> - writel_relaxed(tmp, pll->con_reg);
> -}
> -
> static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> @@ -238,12 +242,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
> (rate->sdiv << PLL35XX_SDIV_SHIFT);
> writel_relaxed(tmp, pll->con_reg);
>
> - /* wait_lock_time if enabled */
> - if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) {
> + /* Wait until the PLL is locked if it is enabled. */
> + if (tmp & BIT(pll->enable_offs)) {
> do {
> cpu_relax();
> tmp = readl_relaxed(pll->con_reg);
> - } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT)));
> + } while (!(tmp & BIT(pll->lock_offs)));
> }
> return 0;
> }
> @@ -252,8 +256,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
> .recalc_rate = samsung_pll35xx_recalc_rate,
> .round_rate = samsung_pll_round_rate,
> .set_rate = samsung_pll35xx_set_rate,
> - .enable = samsung_pll35xx_enable,
> - .disable = samsung_pll35xx_disable,
> + .enable = samsung_pll3xxx_enable,
> + .disable = samsung_pll3xxx_disable,
> };
>
> static const struct clk_ops samsung_pll35xx_clk_min_ops = {
> @@ -275,6 +279,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
> #define PLL36XX_SDIV_SHIFT (0)
> #define PLL36XX_KDIV_SHIFT (0)
> #define PLL36XX_LOCK_STAT_SHIFT (29)
> +#define PLL36XX_ENABLE_SHIFT (31)
>
> static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> @@ -354,10 +359,12 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
> writel_relaxed(pll_con1, pll->con_reg + 4);
>
> /* wait_lock_time */
> - do {
> - cpu_relax();
> - tmp = readl_relaxed(pll->con_reg);
> - } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
> + if (pll_con0 & BIT(pll->enable_offs)) {
> + do {
> + cpu_relax();
> + tmp = readl_relaxed(pll->con_reg);
> + } while (!(tmp & BIT(pll->lock_offs)));
> + }
>
> return 0;
> }
> @@ -366,6 +373,8 @@ static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
> .recalc_rate = samsung_pll36xx_recalc_rate,
> .set_rate = samsung_pll36xx_set_rate,
> .round_rate = samsung_pll_round_rate,
> + .enable = samsung_pll3xxx_enable,
> + .disable = samsung_pll3xxx_disable,
> };
>
> static const struct clk_ops samsung_pll36xx_clk_min_ops = {
> @@ -1288,6 +1297,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> case pll_1450x:
> case pll_1451x:
> case pll_1452x:
> + pll->enable_offs = PLL35XX_ENABLE_SHIFT;
> + pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
> if (!pll->rate_table)
> init.ops = &samsung_pll35xx_clk_min_ops;
> else
> @@ -1306,6 +1317,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> /* clk_ops for 36xx and 2650 are similar */
> case pll_36xx:
> case pll_2650:
> + pll->enable_offs = PLL36XX_ENABLE_SHIFT;
> + pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT;
> if (!pll->rate_table)
> init.ops = &samsung_pll36xx_clk_min_ops;
> else
> --
> 1.9.1
>
>
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 10+ messages in thread