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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDE0MiBTYWx0ZWRfXyBN44okx7A18 OMPIguNMNEw02jt7VfLy96IaLiQVNFtF3PAJwLiuA8V8tkLdgpKbfJqRVpYvCpNkwhCX6rp5IZk djz5QHpvVeWQ5Szcu/ZXlJM+AfDShqHIe3yGPxLk5f+jstyg8cmf53ZPbXRFZYVX/Gq/Ntm1bA+ dGZ8a2AmkbwVMWELdty16Vb8kof6wF6WivMjatb6vDRmT15jcfZKEserHK8B4X8t5FuMZpGu/lW dsDp/sIQYDA8u7XPmqA+mLuZYnN3a+dq7RwRHyvFJid7K9i73t+Tp7eAnrfzKxIUUrNPvc1Cw1j 56WIxFeKVrhuKKPUFOog11hGDZfvLpC3G7eGSNwSpgRMq0VU2CDdVraqO5DTWQRSzTegz0A/Wa9 YjU6OBisaUt/hdN3jskYa5Ib8qEHDgbqO+quPDTrgKvvakXoj/55PsDLr0IPkezi0VNYFMLZ X-Proofpoint-GUID: mMMRmmJ9lhtt5CKxo5trKnLaMwjhA_aS X-Proofpoint-ORIG-GUID: mMMRmmJ9lhtt5CKxo5trKnLaMwjhA_aS X-Authority-Analysis: v=2.4 cv=C8fpyRP+ c=1 sm=1 tr=0 ts=680fbd4c cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Svr01UFivMFfsnZ9dZkWgg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=6H0WHjuAAAAA:8 a=COk6AnOGAAAA:8 a=6dQnf3u2Ryt8jKbU0REA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=Soq9LBFxuPC4vsCAQt-j:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_07,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1011 spamscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504280142 On 4/25/2025 5:42 PM, Luca Weiss wrote: > Compared to the msm-4.19 driver the mainline GDSC driver always sets the > bits for en_rest, en_few & clk_dis, and if those values are not set > per-GDSC in the respective driver then the default value from the GDSC > driver is used. The downstream driver only conditionally sets > clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. > > Correct this situation by explicitly setting those values. For all GDSCs > the reset value of those bits are used. > > Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") > Signed-off-by: Luca Weiss > --- > drivers/clk/qcom/dispcc-sm6350.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c > index e703ecf00e440473156f707498f23cde53fb7e22..b0bd163a449ccd2b27751e32eb17a982facf07d8 100644 > --- a/drivers/clk/qcom/dispcc-sm6350.c > +++ b/drivers/clk/qcom/dispcc-sm6350.c > @@ -681,6 +681,9 @@ static struct clk_branch disp_cc_xo_clk = { > > static struct gdsc mdss_gdsc = { > .gdscr = 0x1004, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0xf, > .pd = { > .name = "mdss_gdsc", > }, > Reviewed-by: Taniya Das