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Date: Wed, 14 Feb 2018 14:03:29 +0900
From: Chanwoo Choi <cw00.choi@samsung.com>
To: Andrzej Hajda <a.hajda@samsung.com>, Sylwester Nawrocki
	<s.nawrocki@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Marek Szyprowski
	<m.szyprowski@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Michael
	Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Kukjin
	Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, "moderated
 list:SAMSUNG SOC CLOCK DRIVERS" <linux-samsung-soc@vger.kernel.org>, "open
 list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 1/7] clk: samsung: exynos3250: fix PLL rates
In-reply-to: <20180213134032.30235-2-a.hajda@samsung.com>
References: <20180213134032.30235-1-a.hajda@samsung.com>
	<CGME20180213134058eucas1p277d1ac59e24cadeea9638abe79f9da27@eucas1p2.samsung.com>
	<20180213134032.30235-2-a.hajda@samsung.com>
List-ID: <linux-clk.vger.kernel.org>

On 2018년 02월 13일 22:40, Andrzej Hajda wrote:
> Declared rates did not match rates generated by PLL.
> As a result driver behaved inconsitently.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos3250.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index 1b81e283f605..ed36728424a2 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -698,7 +698,7 @@ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst =
>  	PLL_36XX_RATE(144000000,  96, 2, 3,     0),
>  	PLL_36XX_RATE( 96000000, 128, 2, 4,     0),
>  	PLL_36XX_RATE( 84000000, 112, 2, 4,     0),
> -	PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
> +	PLL_36XX_RATE( 80000003, 106, 2, 4, 43691),
>  	PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),
>  	PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
>  	PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
> @@ -734,7 +734,7 @@ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst =
>  	PLL_36XX_RATE(148352005,  98, 2, 3, 59070),
>  	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
>  	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
> -	PLL_36XX_RATE( 74176002,  98, 3, 4, 59070),
> +	PLL_36XX_RATE( 74176002,  98, 2, 4, 59070),
>  	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
>  	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
>  	{ /* sentinel */ }
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics