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Date: Wed, 14 Feb 2018 14:07:25 +0900
From: Chanwoo Choi <cw00.choi@samsung.com>
To: Andrzej Hajda <a.hajda@samsung.com>, Sylwester Nawrocki
	<s.nawrocki@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Marek Szyprowski
	<m.szyprowski@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, Michael
	Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Kukjin
	Kim <kgene@kernel.org>, Krzysztof Kozlowski <krzk@kernel.org>, "moderated
 list:SAMSUNG SOC CLOCK DRIVERS" <linux-samsung-soc@vger.kernel.org>, "open
 list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 2/7] clk: samsung: exynos5250: fix PLL rates
In-reply-to: <20180213134032.30235-3-a.hajda@samsung.com>
References: <20180213134032.30235-1-a.hajda@samsung.com>
	<CGME20180213134100eucas1p1a3dd9c27f8779390e77806bc4ecb40ee@eucas1p1.samsung.com>
	<20180213134032.30235-3-a.hajda@samsung.com>
List-ID: <linux-clk.vger.kernel.org>

Hi Andrzej,

On 2018년 02월 13일 22:40, Andrzej Hajda wrote:
> Declared rates did not match rates generated by PLL.
> As a result driver behaved inconsitently.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index 9b073c98a891..923c608b1b95 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -711,13 +711,13 @@ static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
>  	/* sorted in descending order */
>  	/* PLL_36XX_RATE(rate, m, p, s, k) */
>  	PLL_36XX_RATE(192000000, 64, 2, 2, 0),
> -	PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
> +	PLL_36XX_RATE(180633605, 90, 3, 2, 20762),
>  	PLL_36XX_RATE(180000000, 90, 3, 2, 0),
>  	PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
> -	PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
> +	PLL_36XX_RATE(67737602, 90, 2, 4, 20762),
>  	PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
> -	PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
> -	PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
> +	PLL_36XX_RATE(45158401, 90, 3, 4, 20762),
> +	PLL_36XX_RATE(32768001, 131, 3, 5, 4719),
>  	{ },
>  };
>  
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics