From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80E21C433EF for ; Tue, 26 Apr 2022 10:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348374AbiDZKLh (ORCPT ); Tue, 26 Apr 2022 06:11:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348373AbiDZKLH (ORCPT ); Tue, 26 Apr 2022 06:11:07 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3A7020A438; Tue, 26 Apr 2022 02:34:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id D45D81F42EA7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1650965655; bh=jtBKZC8RMt0jLfx45LC4xjlbnrdyLhFIEyBfRCIsU3c=; h=Date:From:Subject:To:Cc:References:In-Reply-To:From; b=EcC8zmqm/98TOeg67Q/LVCohjVTuTwTt4SBXcqP8tjTZHkv3Of0oI8k4aeTi0udqc uT6y59H10IzChaboaSVVAGq/UzdJS0i29i3axjratfqWD7BR8QACinuR1FqxQID/ga rL6A3q5XfpOQOTsmuIRJflpK04MnCYtg54VPtZpoawu0bW9P1OZQKOkmTtslW5VHHF D8Ku4jqS0Ln0NizY9tc9OoJfSgFvorQWwu1Ifxs+I1WCh7JYqBtTwP2S0J2y2+Lr7k XzFcqVsMDgcAwOMEAFwBY6lYrDPg46jNjkIZkVDWCq+uo0XH+caicKAWYt6pC2kD+v IelgBvEo69KEQ== Message-ID: <5a927c06-92af-4608-cb74-eb53a12248d7@collabora.com> Date: Tue, 26 Apr 2022 11:34:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 From: AngeloGioacchino Del Regno Subject: Re: [PATCH V3 05/17] clk: mediatek: reset: Merge and revise reset register function To: Rex-BC Chen , mturquette@baylibre.com, sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: p.zabel@pengutronix.de, chun-jie.chen@mediatek.com, wenst@chromium.org, runyang.chen@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220422060152.13534-1-rex-bc.chen@mediatek.com> <20220422060152.13534-6-rex-bc.chen@mediatek.com> Content-Language: en-US In-Reply-To: <20220422060152.13534-6-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Il 22/04/22 08:01, Rex-BC Chen ha scritto: > There are two versions for clock reset register control of MediaTek > SoCs. The old hardware is one bit per reset control, and does not > have separate registers for bit set, clear and read-back operations. > This matches the scheme supported by the simple reset driver. > > However, because we need to use our data structure "struct mtk_reset", > we can not use the operation of simple reset driver. We keep the > original functions and name this version as "MTK_RST_SIMPLE". > > In this patch: > - Add a version enum to separate different MediaTek reset hardware. > - Merge the reset register function of simple and set_clr into one > function "mtk_register_reset_controller". > - Rename input variable "num_regs" to "rst_set_nr" to avoid > confusion. This variable is used to define the number of reset set. > - Rename "regofs" to "reg_ofs". > - Adjust delaration type for mtk_register_reset_controller(). > > Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno