From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1311130EF84; Mon, 18 May 2026 06:59:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779087560; cv=none; b=CsHL1mjQygEHI5D7NG/xoj5YeGbhdP5iXX2BiJi3bi9HBeLADewcgha5+LAX8nXh7A8WYBcCqZgAyvKw0hprNKC+Y+rnRxLXLUWM1DQ9V0NwdGh8812fLwkaAShWdr65SiHZXA1Dao1Alr3ehuHSjFriZrVPrz7hxt7p4SY9yC4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779087560; c=relaxed/simple; bh=mJa2fIsKGbObKnKnn6ED0BDuVO4OC7l0bfrdvngyKPc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=A0l9kzEKroPleb0sjynrORLw1v+mI10Dxyl8PDNuX9MmGg8K0heII3LkxgHfxI7CJWanJ/trgnKB6A2KFZE2k1ZcXQXdINcMAJqT0O5eOeXhuJsQz2udbLQuGwPg640HUHa8uiqEwhrZ7chnvagBNw81HRLcV3n+YWxaevZ0zZY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Yw5oJjvi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Yw5oJjvi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5A7CC2BCC6; Mon, 18 May 2026 06:59:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779087559; bh=mJa2fIsKGbObKnKnn6ED0BDuVO4OC7l0bfrdvngyKPc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Yw5oJjvia6/E8IR5lymqEjDUR2UACJCBRdK8rSx18wD5GDVUi0cwB1ZUmIkOzUmTG hNZQhl7jCe/e4i+7FsW2pptQP+6dX0EQk/frtH1zUDAdiYE629ezLyI0BIzjiWQtpT gxlk7begv9dK+pL+hzmaSDJTULye09Vu5Xbmmm1nqiNo+K5fRp9Mk3zYn0Q1/hpHiW fM0V2qcgoIvuXSNvEv63pqLygEuxVQjVAqJW2ntsyPyhL7+UutFDsxDPi4zLXLjgLq K1oLhOTMF7k6IG/oqK16rJN2eP8xMcPw+XugivlByxO8WjwiZxsGdcdmyRZYCwhsYl EQ8bNGUBPty6A== Message-ID: <5ad0685b-9ba4-4ada-863f-4e5a24a761ff@kernel.org> Date: Mon, 18 May 2026 08:59:14 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] dt-bindings: clock: qcom: Add QREF regulator supplies for glymur To: Qiang Yu Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, krishna.chundru@oss.qualcomm.com References: <20260506-qref_vote_0506-v3-0-5ab71d2e6f16@oss.qualcomm.com> <20260506-qref_vote_0506-v3-1-5ab71d2e6f16@oss.qualcomm.com> <20260514-outgoing-literate-dove-2e2a73@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/05/2026 05:35, Qiang Yu wrote: > On Sun, May 17, 2026 at 10:28:48AM +0200, Krzysztof Kozlowski wrote: >> On 17/05/2026 07:58, Qiang Yu wrote: >>> On Thu, May 14, 2026 at 12:35:19PM +0200, Krzysztof Kozlowski wrote: >>>> On 14/05/2026 12:22, Krzysztof Kozlowski wrote: >>>>> On Wed, May 06, 2026 at 01:43:51AM -0700, Qiang Yu wrote: >>>>>> Add regulator supply properties for the Glymur TCSR QREF/REFGEN blocks >>>>>> required by clkref clocks. >>>>>> >>>>>> The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common >>>>>> QREF TX/RPT/RX components, while SoC-specific topology and instance count >>>>>> differ. Document them here for qcom,glymur-tcsr. >>>>>> >>>>>> Signed-off-by: Qiang Yu >>>>>> --- >>>>>> .../bindings/clock/qcom,sm8550-tcsr.yaml | 57 ++++++++++++++++++++++ >>>>>> 1 file changed, 57 insertions(+) >>>>>> >>>>>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>>>>> index 1ccdf4b0f5dd..57921cb63230 100644 >>>>>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>>>>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml >>>>>> @@ -51,6 +51,63 @@ properties: >>>>>> '#reset-cells': >>>>>> const: 1 >>>>>> >>>>>> + vdda-refgen-0p9-supply: true >>>>>> + vdda-refgen-1p2-supply: true >>>>>> + vdda-qrefrx0-0p9-supply: true >>>>>> + vdda-qrefrx1-0p9-supply: true >>>>>> + vdda-qrefrx2-0p9-supply: true >>>>>> + vdda-qrefrx4-0p9-supply: true >>>>>> + vdda-qrefrx5-0p9-supply: true >>>>>> + vdda-qreftx0-0p9-supply: true >>>>>> + vdda-qreftx0-1p2-supply: true >>>>>> + vdda-qreftx1-0p9-supply: true >>>>>> + vdda-qrefrpt0-0p9-supply: true >>>>>> + vdda-qrefrpt1-0p9-supply: true >>>>>> + vdda-qrefrpt2-0p9-supply: true >>>>>> + vdda-qrefrpt3-0p9-supply: true >>>>>> + vdda-qrefrpt4-0p9-supply: true >>>>> >>>>> Either I do not understand your previous explanation: >>>>> CXO -> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 -> PCIe4_PHY >>>>> >>>>> or this is still wrong. There is no TCSR here, so this proves nothing. >>>>> If TCSR is TX0, then you do not have five of them... >>>>> >>>>> My previous comment stay - you are not describing the actual hardware >>>>> here. >>>> >>>> And it should not be my task BUT YOURS to verify this in hardware >>>> programming guide or manual, but nevertheless I did verify and the >>>> manual DOES NOT mention these supplies. For Glymur, it mentions 8 reset >>>> ports and 5 clock ports. >>>> >>>> No supplies at all. >>>> >>>> Then I went to QREF and it does mention few supplies but completely >>>> different, like mx, cx, px 0.88 and px1.2, so none of this matches QREF >>>> either. >>>> >>> >>> Honestly, I couldn't find QREF LDO-related information in HPG either. >>> However, you can find it on IPCAT. For example, in the glymur power grid, >>> these LDOs are clearly documented under the LDOs required by each PHY, >> >> How is that relevant here? This is not PHY here. You are adding supplies >> to TCSR. Do you understand what a supply is? >> > > I'm telling you the fact that I see from power grid table. So you see supplies in phy, then add them to the phy. Best regards, Krzysztof