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Sat, 06 Dec 2025 03:19:20 -0800 (PST) Message-ID: <5afbf96a-c87f-43cb-8cd1-d7c9970bfd07@tuxon.dev> Date: Sat, 6 Dec 2025 13:19:19 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility To: Conor Dooley , linux-kernel@vger.kernel.org Cc: Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Pierre-Henry Moussay References: <20251121-tartar-drew-ba31c5ec9192@spud> <20251121-trade-slacked-5fc7c1139cb2@spud> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <20251121-trade-slacked-5fc7c1139cb2@spud> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/21/25 15:44, Conor Dooley wrote: > From: Pierre-Henry Moussay > > pic64gx SoC Clock Conditioning Circuitry is compatibles > with the Polarfire SoC > > Signed-off-by: Pierre-Henry Moussay > Acked-by: Conor Dooley > Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea > --- > .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > index f1770360798f..9a6b50527c42 100644 > --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml > @@ -17,7 +17,11 @@ description: | > > properties: > compatible: > - const: microchip,mpfs-ccc > + oneOf: > + - items: > + - const: microchip,pic64gx-ccc > + - const: microchip,mpfs-ccc > + - const: microchip,mpfs-ccc > > reg: > items: