From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E45C64ED8 for ; Mon, 13 Feb 2023 06:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229675AbjBMGCi (ORCPT ); Mon, 13 Feb 2023 01:02:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229561AbjBMGCg (ORCPT ); Mon, 13 Feb 2023 01:02:36 -0500 Received: from codeconstruct.com.au (pi.codeconstruct.com.au [203.29.241.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61405EFA5; Sun, 12 Feb 2023 22:02:34 -0800 (PST) Received: by codeconstruct.com.au (Postfix, from userid 10000) id C596C20260; Mon, 13 Feb 2023 14:02:32 +0800 (AWST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1676268152; bh=N5/5jC61xpURI7FZgciBaBll37+K+6NjCpm4F8ofxhA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=B2ps0aHCBqBGWWGrvyKafGhrBRfVS54QYM830O0RC5SWLQn92riJ1HlS88ijHlDvL wqANRbK1LPumrKwNsy4JojxxXXdOn1CFvvdic/oYtMysA6ZbV+/3eFpHWR4mtgGjUw vUnAAuVi9R6QUUXgKBxZ4V4Tao5q6KSw2KKctttyXu68aaC+RVQVzaCO/mt3cQ+M92 PQj1Z48T4JA1UcgmghWkD5MDMd4/WcmoSWwG678W6d+qvMmcU58S6lkqFXmRylUDIP tqmyd3vTZZKr2KR3FDiikftpAg5I7J6GuE4vE5XOHhCerIb1leLJkzrRS00OgNn6PU 4ELCv6AzKiQzQ== From: Jeremy Kerr To: linux-aspeed@lists.ozlabs.org, linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski , Michael Turquette , Rob Herring , Stephen Boyd , Dylan Hung , Joel Stanley , Andrew Jeffery Subject: [PATCH v2 2/3] clk: aspeed: Add full configs for i3c clocks Date: Mon, 13 Feb 2023 14:02:07 +0800 Message-Id: <5ee4ade6820a9db8dc9c20bb39fd8a4c4cd7c2a6.1676267865.git.jk@codeconstruct.com.au> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The current ast2600 i3c clock definitions are top-level (rather than based on their actual hw sources: either HCLK or APLL), and include a couple of definitions for (non-existent) i3c6 and i3c7. This change re-parents these to the main i3c clock, explicitly sourced from the APLL rather than whatever G6_CLK_SELECTION5 was last set to. We also remove the i3c6 and i3c7 definitions. This change is a partial cherry-pick and rework of ed44b8cdfdb and 1a35eb926d7 from Aspeed's own tree, originally by Dylan Hung . Signed-off-by: Jeremy Kerr --- drivers/clk/clk-ast2600.c | 38 ++++++++++++++++++----- include/dt-bindings/clock/ast2600-clock.h | 3 +- 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c index 1f08ff3c60fa..45549cb18107 100644 --- a/drivers/clk/clk-ast2600.c +++ b/drivers/clk/clk-ast2600.c @@ -4,6 +4,7 @@ #define pr_fmt(fmt) "clk-ast2600: " fmt +#include #include #include #include @@ -32,6 +33,18 @@ #define ASPEED_G6_CLK_SELECTION1 0x300 #define ASPEED_G6_CLK_SELECTION2 0x304 #define ASPEED_G6_CLK_SELECTION4 0x310 +#define ASPEED_G6_CLK_SELECTION5 0x314 +#define I3C_CLK_SELECTION BIT(31) +#define I3C_CLK_SELECT_HCLK 0 +#define I3C_CLK_SELECT_APLL_DIV 1 +#define APLL_DIV_SELECTION GENMASK(30, 28) +#define APLL_DIV_2 0b001 +#define APLL_DIV_3 0b010 +#define APLL_DIV_4 0b011 +#define APLL_DIV_5 0b100 +#define APLL_DIV_6 0b101 +#define APLL_DIV_7 0b110 +#define APLL_DIV_8 0b111 #define ASPEED_HPLL_PARAM 0x200 #define ASPEED_APLL_PARAM 0x210 @@ -97,14 +110,13 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = { [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ /* Reserved 38 RSA: no longer used */ /* Reserved 39 */ - [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ - [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ - [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ - [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ - [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ - [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ - [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ - [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ + [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", "i3cclk", 0 }, /* I3C0 */ + [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", "i3cclk", 0 }, /* I3C1 */ + [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", "i3cclk", 0 }, /* I3C2 */ + [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", "i3cclk", 0 }, /* I3C3 */ + [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", "i3cclk", 0 }, /* I3C4 */ + [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", "i3cclk", 0 }, /* I3C5 */ + /* Reserved: 46 & 47 */ [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ @@ -775,6 +787,16 @@ static void __init aspeed_g6_cc(struct regmap *map) /* USB 2.0 port1 phy 40MHz clock */ hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; + + /* i3c clock: source from apll, divide by 8 */ + regmap_read(map, ASPEED_G6_CLK_SELECTION5, &val); + val &= ~(I3C_CLK_SELECTION | APLL_DIV_SELECTION); + val |= FIELD_PREP(I3C_CLK_SELECTION, I3C_CLK_SELECT_APLL_DIV); + val |= FIELD_PREP(APLL_DIV_SELECTION, APLL_DIV_8); + regmap_write(map, ASPEED_G6_CLK_SELECTION5, val); + + hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8); + aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw; }; static void __init aspeed_g6_cc_init(struct device_node *np) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index d8b0db2f7a7d..600549d7bee8 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -57,8 +57,6 @@ #define ASPEED_CLK_GATE_I3C3CLK 40 #define ASPEED_CLK_GATE_I3C4CLK 41 #define ASPEED_CLK_GATE_I3C5CLK 42 -#define ASPEED_CLK_GATE_I3C6CLK 43 -#define ASPEED_CLK_GATE_I3C7CLK 44 #define ASPEED_CLK_GATE_FSICLK 45 @@ -87,6 +85,7 @@ #define ASPEED_CLK_MAC2RCLK 68 #define ASPEED_CLK_MAC3RCLK 69 #define ASPEED_CLK_MAC4RCLK 70 +#define ASPEED_CLK_I3C 74 /* Only list resets here that are not part of a gate */ #define ASPEED_RESET_ADC 55 -- 2.39.1