[PATCH 01/13] clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks

Taniya Das
2024-05-31T09:03:39Z

The UFS hw ctl clocks are not being used on SA8775P, hence remove
support for the same.

Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
drivers/clk/qcom/gcc-sa8775p.c | 111 +--------------------------------
1 file changed, 2 insertions(+), 109 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 5bcbfbf52cb9..7bb7aa3a7be5 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -1,14 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/

-#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -1737,26 +1735,6 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
},
};

-static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
- .halt_reg = 0x830d4,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x830d4,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x830d4,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
.halt_reg = 0x1c05c,
.halt_check = BRANCH_HALT_VOTED,
@@ -3809,26 +3787,6 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
},
};

-static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
- .halt_reg = 0x83018,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x83018,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x83018,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_axi_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x8306c,
.halt_check = BRANCH_HALT_VOTED,
@@ -3849,26 +3807,6 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
},
};

-static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
- .halt_reg = 0x8306c,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x8306c,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x8306c,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x830a4,
.halt_check = BRANCH_HALT_VOTED,
@@ -3889,26 +3827,6 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
},
};

-static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
- .halt_reg = 0x830a4,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x830a4,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x830a4,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x83028,
.halt_check = BRANCH_HALT_DELAY,
@@ -3983,26 +3901,6 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
},
};

-static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
- .halt_reg = 0x83064,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x83064,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x83064,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x1c018,
.halt_check = BRANCH_HALT,
@@ -4379,7 +4277,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
- [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
@@ -4569,13 +4466,10 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
- [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
- [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
- [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
@@ -4584,7 +4478,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
- [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
--
2.17.1