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Wed, 21 Aug 2024 08:25:07 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47L8P5j5025859 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Aug 2024 08:25:05 GMT Received: from [10.216.8.12] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 21 Aug 2024 01:25:00 -0700 Message-ID: <6016f2ec-6918-471c-a8dc-0aa98fc2b824@quicinc.com> Date: Wed, 21 Aug 2024 13:54:57 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] clk: qcom: Add support for Global Clock Controller on QCS8300 To: Andrew Lunn CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , "Ajit Pandey" , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , References: <20240820-qcs8300-gcc-v1-0-d81720517a82@quicinc.com> <20240820-qcs8300-gcc-v1-2-d81720517a82@quicinc.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 90ASgeUzY0yu7HUlsbJzQvY0H5JxiK8b X-Proofpoint-GUID: 90ASgeUzY0yu7HUlsbJzQvY0H5JxiK8b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-21_07,2024-08-19_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 clxscore=1011 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408210060 On 8/20/2024 7:36 PM, Andrew Lunn wrote: >> +static int gcc_qcs8300_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; >> + int ret; >> + >> + regmap = qcom_cc_map(pdev, &gcc_qcs8300_desc); >> + if (IS_ERR(regmap)) >> + return PTR_ERR(regmap); >> + >> + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, >> + ARRAY_SIZE(gcc_dfs_clocks)); >> + if (ret) >> + return ret; >> + >> + /* Keep some clocks always enabled */ >> + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ > > It would be good to document why. Why does the camera driver not > enable the clock when it loads? > >> + qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ > > Why cannot the display driver enable the clock when it loads? > These clocks require for DISPCC and CAMCC drivers for register access, hence kept enabled at GCC driver probe. The same approach is followed for all the targets. Thanks, Imran > Andrew