Re: [PATCH v4 6/7] dt-bindings: clock: qcom: document the Glymur Global Clock Controller

[Taniya Das <taniya.das@oss.qualcomm.com>]

>>> +      - description: USB 2 Phy PIPEGMUX clock source
>>> +      - description: USB 2 Phy SYS PCIE PIPEGMUX clock source
>>> +      - description: PCIe 3a pipe clock
>>> +      - description: PCIe 4b pipe clock

Bjorn, will fix this typo and the below one as well.

>>> +      - description: PCIe 4 pipe clock
>>> +      - description: PCIe 5 pipe clock
>>> +      - description: PCIe 6 pipe clock
>>> +      - description: PCIe 6b pipe clock

Got this extra due to huge list of external clocks.

>>
>> When I look at the documentation, we seem to have pipe clocks for pcie
>> 0, 1, 2, 3a, 3b, 4, 5, and 6. And this seems to better match the clock
>> defines below as well...
>>
> 
> Bjorn, the PCIE 0, 1, 2 are connected to USB4 PHY 0/1/2 pcie pipe clock
> source.
> 
>> Can you please confirm that the inputs you have listed here are complete
>> and correct? (It's not going to be possible to add things in the middle
>> later and adding 0, 1, and 2 at the bottom will not sit well with my
>> OCD).
>>
> 
> These are the complete list of external clocks and nothing else is required.
> 
>> Regards,
>> Bjorn
>>
>>> +      - description: QUSB4 0 PHY RX 0 clock source
>>> +      - description: QUSB4 0 PHY RX 1 clock source
>>> +      - description: QUSB4 1 PHY RX 0 clock source
>>> +      - description: QUSB4 1 PHY RX 1 clock source
>>> +      - description: QUSB4 2 PHY RX 0 clock source
>>> +      - description: QUSB4 2 PHY RX 1 clock source
>>> +      - description: UFS PHY RX Symbol 0 clock source
>>> +      - description: UFS PHY RX Symbol 1 clock source
>>> +      - description: UFS PHY TX Symbol 0 clock source
>>> +      - description: USB3 PHY 0 pipe clock source
>>> +      - description: USB3 PHY 1 pipe clock source
>>> +      - description: USB3 PHY 2 pipe clock source
>>> +      - description: USB3 UNI PHY pipe 0 clock source
>>> +      - description: USB3 UNI PHY pipe 1 clock source
>>> +      - description: USB4 PHY 0 pcie pipe clock source
>>> +      - description: USB4 PHY 0 Max pipe clock source
>>> +      - description: USB4 PHY 1 pcie pipe clock source
>>> +      - description: USB4 PHY 1 Max pipe clock source
>>> +      - description: USB4 PHY 2 pcie pipe clock source
>>> +      - description: USB4 PHY 2 Max pipe clock source
>>> +
>>> +required:
>>> +  - compatible
>>> +  - clocks
>>> +  - '#power-domain-cells'
>>> +
>>> +allOf:
>>> +  - $ref: qcom,gcc.yaml#
>>> +
>>> +unevaluatedProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/clock/qcom,rpmh.h>
>>> +    clock-controller@100000 {
>>> +      compatible = "qcom,glymur-gcc";
>>> +      reg = <0x100000 0x1f9000>;
>>> +      clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> +               <&rpmhcc RPMH_CXO_CLK_A>,
>>> +               <&sleep_clk>,
>>> +               <&usb_0_phy_dp0_gmux>,
>>> +               <&usb_0_phy_dp1_gmux>,
>>> +               <&usb_0_phy_pcie_pipegmux>,
>>> +               <&usb_0_phy_pipegmux>,
>>> +               <&usb_0_phy_sys_pcie_pipegmux>,
>>> +               <&usb_1_phy_dp0_gmux_2>,
>>> +               <&usb_1_phy_dp1_gmux_2>,
>>> +               <&usb_1_phy_pcie_pipegmux>,
>>> +               <&usb_1_phy_pipegmux>,
>>> +               <&usb_1_phy_sys_pcie_pipegmux>,
>>> +               <&usb_2_phy_dp0_gmux 2>,
>>> +               <&usb_2_phy_dp1_gmux 2>,
>>> +               <&usb_2_phy_pcie_pipegmux>,
>>> +               <&usb_2_phy_pipegmux>,
>>> +               <&usb_2_phy_sys_pcie_pipegmux>,
>>> +               <&pcie_3a_pipe>, <&pcie_4b_pipe>,

Fix here.

>>> +               <&pcie_4_pipe>, <&pcie_5_pipe>,
>>> +               <&pcie_6_pipe>, <&pcie_6b_pipe>,

Fix here as well.

>>> +               <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
>>> +               <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
>>> +               <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
>>> +               <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
>>> +               <&ufs_phy_tx_symbol_0>,
>>> +               <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
>>> +               <&usb3_phy_2_pipe>,
>>> +               <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
>>> +               <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
>>> +               <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
>>> +               <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
>>> +      #clock-cells = <1>;
>>> +      #reset-cells = <1>;
>>> +      #power-domain-cells = <1>;
>>> +    };
>>> +

-- 
Thanks,
Taniya Das