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[93.34.90.105]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431182d790fsm19521105e9.6.2024.10.10.08.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 08:46:44 -0700 (PDT) Message-ID: <6707f6e4.050a0220.97bc9.6760@mx.google.com> X-Google-Original-Message-ID: Date: Thu, 10 Oct 2024 17:46:41 +0200 From: Christian Marangi To: AngeloGioacchino Del Regno Cc: Stephen Boyd , Conor Dooley , Felix Fietkau , Krzysztof Kozlowski , Lorenzo Bianconi , Michael Turquette , Philipp Zabel , Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, upstream@airoha.com, linux-arm-kernel@lists.infradead.org, lorenzo.bianconi83@gmail.com Subject: Re: [PATCH v2 0/7] clk: en7523: Update register mapping for EN7581 References: <20240903-clk-en7581-syscon-v2-0-86fbe2fc15c3@kernel.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Oct 09, 2024 at 04:24:55PM -0700, Stephen Boyd wrote: > Quoting Lorenzo Bianconi (2024-10-01 01:30:59) > > On Sep 03, Lorenzo Bianconi wrote: > > > Map all clock-controller memory region in a single block for EN7581 SoC. > > > Introduce chip_scu regmap pointer since EN7581 SoC will access chip-scu > > > memory area through a syscon node. > > > REG_PCIE*_MEM and REG_PCIE*_MEM_MASK registers (PBUS_CSR) are not > > > part of the scu block on the EN7581 SoC and they are used to select the > > > PCIE ports on the PBUS, so configure them via in the PCIE host driver. > > > This series does not introduce any backward incompatibility since the > > > dts for EN7581 SoC is not upstream yet. > > > > Hi, > > > > any update on this series? Are we supposed to do something? > > > > I was waiting for review from someone like AngeloGioacchino. AngeloGioacchino any chance you can help with this? It's sad that these simple changes stalled and are currently stopping upstream of the EN7581 SoC :( -- Ansuel