From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 521BCC54EE9 for ; Fri, 2 Sep 2022 06:40:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235487AbiIBGj5 (ORCPT ); Fri, 2 Sep 2022 02:39:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235470AbiIBGjz (ORCPT ); Fri, 2 Sep 2022 02:39:55 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47750D56; Thu, 1 Sep 2022 23:39:46 -0700 (PDT) X-UUID: c05eac422097471c872056318a83e103-20220902 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; 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Fri, 02 Sep 2022 14:39:39 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 2 Sep 2022 14:39:38 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 2 Sep 2022 14:39:37 +0800 Message-ID: <67237f85d1c4bc72906848d811988209d0112c06.camel@mediatek.com> Subject: Re: [PATCH 2/4] dt-bindings: arm: mediatek: Add new bindings of MediaTek frequency hopping From: Johnson Wang To: Krzysztof Kozlowski , , , , CC: , , , , , , Edward-JW Yang Date: Fri, 2 Sep 2022 14:39:38 +0800 In-Reply-To: References: <20220831124850.7748-1-johnson.wang@mediatek.com> <20220831124850.7748-3-johnson.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Wed, 2022-08-31 at 16:19 +0300, Krzysztof Kozlowski wrote: > On 31/08/2022 15:48, Johnson Wang wrote: > > Add the new binding documentation for MediaTek frequency hopping > > and spread spectrum clocking control. > > > > Co-developed-by: Edward-JW Yang > > Signed-off-by: Edward-JW Yang > > Signed-off-by: Johnson Wang > > --- > > .../bindings/arm/mediatek/mediatek,fhctl.yaml | 49 > > +++++++++++++++++++ > > 1 file changed, 49 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yam > > l > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yam > > l > > new file mode 100644 > > index 000000000000..c5d76410538b > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,fhctl.yam > > l > > @@ -0,0 +1,49 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,fhctl.yaml*__;Iw!!CTRNKA9wMg0ARbw!ysl-bMp7yP9Ym70o6EVB8A36MBxcXGap8doEKR_SbaAQSy8-_RU5jvrWTjzETut_6eXNGut4j-3dY0q7xJdpQbmaOw$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!ysl-bMp7yP9Ym70o6EVB8A36MBxcXGap8doEKR_SbaAQSy8-_RU5jvrWTjzETut_6eXNGut4j-3dY0q7xJezt7_RBw$ > > > > + > > +title: MediaTek frequency hopping and spread spectrum clocking > > control > > + > > +maintainers: > > + - Edward-JW Yang > > + > > +description: | > > + Frequency hopping control (FHCTL) is a piece of hardware that > > control > > + some PLLs to adopt "hopping" mechanism to adjust their > > frequency. > > + Spread spectrum clocking (SSC) is another function provided by > > this hardware. > > + > > +properties: > > + compatible: > > + const: mediatek,fhctl > > You need SoC/device specific compatibles. Preferably only SoC > specific, > without generic fallback, unless you can guarantee (while > representing > MediaTek), that generic fallback will cover all of their SoCs? > Hi Krzysztof, At this moment, we plan to support FHCTL feature for MT8186 only. If you prefer SoC-specific compatble, we will improve that in the next version. Thanks for your suggestion. BRs, Johnson Wang > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,hopping-ssc-percents: > > + description: | > > + Determine the enablement of frequency hopping feature and > > the percentage > > + of spread spectrum clocking for PLLs. > > + $ref: /schemas/types.yaml#/definitions/uint32-matrix > > + items: > > + items: > > + - description: PLL id that is expected to enable frequency > > hopping. > > So the clocks are indices from some specific, yet unnamed > clock-controller? This feels hacky. You should rather take here clock > phandles (1) or integrate it into specific clock controller (2). The > reason is that either your device does something on top of existing > clocks (option 1, thus it takes clock as inputs) or it modifies > existing > clocks (option 2, thus it is integral part of clock-controller). > > > Best regards, > Krzysztof