From: Samuel Holland <samuel.holland@sifive.com>
To: Chen Wang <unicorn_wang@outlook.com>,
Conor Dooley <conor@kernel.org>, Chen Wang <unicornxw@gmail.com>
Cc: aou@eecs.berkeley.edu, chao.wei@sophgo.com,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com
Subject: Re: [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC
Date: Tue, 14 Nov 2023 21:15:17 -0500 [thread overview]
Message-ID: <68220eb6-8a20-42d4-83e5-d0d45b2f1404@sifive.com> (raw)
In-Reply-To: <PN3P287MB032447BC501261D47E8E3124FEB1A@PN3P287MB0324.INDP287.PROD.OUTLOOK.COM>
On 2023-11-14 7:34 PM, Chen Wang wrote:
> On 2023/11/15 1:31, Conor Dooley wrote:
>> On Mon, Nov 13, 2023 at 09:20:11PM +0800, Chen Wang wrote:
>>> From: Chen Wang <unicorn_wang@outlook.com>
>>>
>>> Add clock generator node to device tree for SG2042, and enable clock for
>>> uart0.
>>>
>>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>>> ---
>>> arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi | 76 ++++++++++++++++++++
>> There's no need to create an entirely new file for this.
> Agree, I will merge this into sg2042.dtsi in next revision.
>>
>>> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 10 +++
>>> 2 files changed, 86 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>> b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>> new file mode 100644
>>> index 000000000000..66d2723fab35
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-clock.dtsi
>>> @@ -0,0 +1,76 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/*
>>> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
>>> + */
>>> +
>>> +/ {
>>> + cgi: oscillator {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <25000000>;
>>> + clock-output-names = "cgi";
>>> + #clock-cells = <0>;
>>> + };
>> What actually is this oscillator?
>> Is it provided by another clock controller on the SoC, or is it provided
>> by an oscillator on the board?
>
> This oscillator is an individual ic chip outside the SoC on the board, that's
> why I list it outside soc node.
>
> Actually the "cgi" is abbrevation for "Clock Generation IC chip".
Since the oscillator is outside the SoC, this node (or at least its
clock-frequency property) belongs in the board devicetree, not the SoC .dtsi.
See [1].
Regards,
Samuel
[1]:
https://lore.kernel.org/linux-riscv/b5401052-e803-9788-64d6-82b2737533ce@linaro.org/
next prev parent reply other threads:[~2023-11-15 2:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-13 13:16 [PATCH 0/5] riscv: sophgo: add clock support for sg2042 Chen Wang
2023-11-13 13:18 ` [PATCH 1/5] dt-bindings: clock: sophgo: Add SG2042 clock definitions Chen Wang
2023-11-14 17:35 ` Conor Dooley
2023-11-15 1:12 ` Chen Wang
2023-11-13 13:19 ` [PATCH 2/5] dt-bindings: soc: sophgo: Add Sophgo syscon module Chen Wang
2023-11-14 17:40 ` Conor Dooley
2023-11-15 1:27 ` Chen Wang
2023-11-16 18:13 ` Rob Herring
2023-11-13 13:19 ` [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings Chen Wang
2023-11-16 18:18 ` Rob Herring
2023-11-17 0:34 ` Chen Wang
2023-11-13 13:19 ` [PATCH 4/5] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2023-11-15 13:02 ` kernel test robot
2023-11-19 11:11 ` kernel test robot
2023-11-13 13:20 ` [PATCH 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
2023-11-14 17:31 ` Conor Dooley
2023-11-15 1:34 ` Chen Wang
2023-11-15 2:15 ` Samuel Holland [this message]
2023-11-15 2:34 ` Chen Wang
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