Re: [PATCH 08/10] arm64: dts: qcom: sc8180x: Add USB MP controller and phys

Konrad Dybcio
2024-05-28T12:53:15Z

On 5/25/24 20:04, Bjorn Andersson wrote:
> From: Bjorn Andersson <quic_bjorande@quicinc.com>
>
> The SC8180X platform comes with a multiport DWC3 controller with two
> ports, each connected to a pair of HighSpeed and QMP SuperSpeed PHYs.
>
> Describe these blocks.
>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 146 ++++++++++++++++++++++++++++++++++
> 1 file changed, 146 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> index 9ef3fa40e1d8..0950dc7adb20 100644
> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> @@ -2511,6 +2511,34 @@ usb_sec_hsphy: phy@88e3000 {
> status = "disabled";
> };
>
> + usb_mp0_hsphy: phy@88e4000 {

Even though the register names are MPn, I think this is a bit confusing..

There's only one MP controller, so perhaps usb_mp_hsphy0?

[...]

> + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;

PIPE_1_CLK

> + clock-names = "aux", "ref", "com_aux", "pipe";

This could be a vertical list

> +
> + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
> + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
> + reset-names = "phy", "phy_phy";
> +
> + power-domains = <&gcc USB30_MP_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "usb2_phy1_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> usb_sec_qmpphy: phy@88ee000 {
> compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
> reg = <0 0x088ee000 0 0x18c>,
> @@ -2662,6 +2738,76 @@ gem_noc: interconnect@9680000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + usb_mp: usb@a4f8800 {
> + compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
> + reg = <0 0x0a4f8800 0 0x400>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;

This is used by the secondary DWC3 (non-MP). Are you sure?

Actually, are we sure that these clocks are really supplying the DWC3s?

> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "xo";
> +
> + interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event_1", "pwr_event_2",
> + "hs_phy_1", "hs_phy_2",
> + "dp_hs_phy_1", "dm_hs_phy_1",
> + "dp_hs_phy_2", "dm_hs_phy_2",
> + "ss_phy_1", "ss_phy_2";
> +
> + power-domains = <&gcc USB30_MP_GDSC>;
> +
> + resets = <&gcc GCC_USB30_MP_BCR>;
> +
> + status = "disabled";
> +
> + usb_mp_dwc3: usb@a400000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a400000 0 0xcd00>;
> + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x60 0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;

sa8195-usb.dtsi lists a bunch more fluff:

snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,ssp-u3-u0-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u3_susphy_quirk;
snps,force-gen1;
maximum-speed = "super-speed";

the irq numbers look good

Konrad