Re: [PATCH v3 3/3] clk: samsung: exynos990: Fix PERIS gate clock parents

[Denzeel Oliva <wachiturroxd150@gmail.com>]

On Sat, Jun 13, 2026, Sashiko AI wrote:
> Does reordering the mout_peris_clk_peris_gic_p array break the hardware
> register mapping?
>
> In the Exynos clock framework, the indices of the PNAME array correspond
> directly to the hardware multiplexer register bit values...

The reorder does not break the mapping — it corrects it. The original
upstream PNAME order was a porting bug that inverted the parents.

The downstream Exynos9830 source confirms the hardware register encoding
(drivers/soc/samsung/cal-if/exynos9830/cmucal-node.c:1093-1096):

  enum clk_id cmucal_mux_clk_peris_gic_parents[] = {
      MUX_CLKCMU_PERIS_BUS_USER,   // index 0 → mux value 0
      OSCCLK_PERIS,                 // index 1 → mux value 1
  };

So hardware mux value 0 selects MUX_CLKCMU_PERIS_BUS_USER (upstream:
mout_peris_bus_user), not oscclk. The original upstream had these
swapped, which would cause clk_set_parent() to write the wrong mux
register value.

This patch fixes that inversion.