From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down
Date: Tue, 27 Dec 2022 13:00:57 +0100 [thread overview]
Message-ID: <6b294284-03a2-f109-ed5f-5e0f3fbc00a0@linaro.org> (raw)
In-Reply-To: <20221227013225.2847382-10-dmitry.baryshkov@linaro.org>
On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the PLL declrataions, so that we
> can use pll hw clock fields in the next commit.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/mmcc-apq8084.c | 200 ++++++++++++++++----------------
> 1 file changed, 100 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index 4acbcb43927f..fee7c767132d 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -40,6 +40,106 @@ enum {
> P_MMSLEEP,
> };
>
> +static struct clk_pll mmpll0 = {
> + .l_reg = 0x0004,
> + .m_reg = 0x0008,
> + .n_reg = 0x000c,
> + .config_reg = 0x0014,
> + .mode_reg = 0x0000,
> + .status_reg = 0x001c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll0",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap mmpll0_vote = {
> + .enable_reg = 0x0100,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "mmpll0_vote",
> + .parent_names = (const char *[]){ "mmpll0" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll1 = {
> + .l_reg = 0x0044,
> + .m_reg = 0x0048,
> + .n_reg = 0x004c,
> + .config_reg = 0x0050,
> + .mode_reg = 0x0040,
> + .status_reg = 0x005c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll1",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_regmap mmpll1_vote = {
> + .enable_reg = 0x0100,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "mmpll1_vote",
> + .parent_names = (const char *[]){ "mmpll1" },
> + .num_parents = 1,
> + .ops = &clk_pll_vote_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll2 = {
> + .l_reg = 0x4104,
> + .m_reg = 0x4108,
> + .n_reg = 0x410c,
> + .config_reg = 0x4110,
> + .mode_reg = 0x4100,
> + .status_reg = 0x411c,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll2",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll3 = {
> + .l_reg = 0x0084,
> + .m_reg = 0x0088,
> + .n_reg = 0x008c,
> + .config_reg = 0x0090,
> + .mode_reg = 0x0080,
> + .status_reg = 0x009c,
> + .status_bit = 17,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll3",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> +static struct clk_pll mmpll4 = {
> + .l_reg = 0x00a4,
> + .m_reg = 0x00a8,
> + .n_reg = 0x00ac,
> + .config_reg = 0x00b0,
> + .mode_reg = 0x0080,
> + .status_reg = 0x00bc,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "mmpll4",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_pll_ops,
> + },
> +};
> +
> static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
> { P_XO, 0 },
> { P_MMPLL0, 1 },
> @@ -212,106 +312,6 @@ static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
> "sleep_clk_src",
> };
>
> -static struct clk_pll mmpll0 = {
> - .l_reg = 0x0004,
> - .m_reg = 0x0008,
> - .n_reg = 0x000c,
> - .config_reg = 0x0014,
> - .mode_reg = 0x0000,
> - .status_reg = 0x001c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll0",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap mmpll0_vote = {
> - .enable_reg = 0x0100,
> - .enable_mask = BIT(0),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmpll0_vote",
> - .parent_names = (const char *[]){ "mmpll0" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll1 = {
> - .l_reg = 0x0044,
> - .m_reg = 0x0048,
> - .n_reg = 0x004c,
> - .config_reg = 0x0050,
> - .mode_reg = 0x0040,
> - .status_reg = 0x005c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll1",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_regmap mmpll1_vote = {
> - .enable_reg = 0x0100,
> - .enable_mask = BIT(1),
> - .hw.init = &(struct clk_init_data){
> - .name = "mmpll1_vote",
> - .parent_names = (const char *[]){ "mmpll1" },
> - .num_parents = 1,
> - .ops = &clk_pll_vote_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll2 = {
> - .l_reg = 0x4104,
> - .m_reg = 0x4108,
> - .n_reg = 0x410c,
> - .config_reg = 0x4110,
> - .mode_reg = 0x4100,
> - .status_reg = 0x411c,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll2",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll3 = {
> - .l_reg = 0x0084,
> - .m_reg = 0x0088,
> - .n_reg = 0x008c,
> - .config_reg = 0x0090,
> - .mode_reg = 0x0080,
> - .status_reg = 0x009c,
> - .status_bit = 17,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll3",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> -static struct clk_pll mmpll4 = {
> - .l_reg = 0x00a4,
> - .m_reg = 0x00a8,
> - .n_reg = 0x00ac,
> - .config_reg = 0x00b0,
> - .mode_reg = 0x0080,
> - .status_reg = 0x00bc,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "mmpll4",
> - .parent_names = (const char *[]){ "xo" },
> - .num_parents = 1,
> - .ops = &clk_pll_ops,
> - },
> -};
> -
> static struct clk_rcg2 mmss_ahb_clk_src = {
> .cmd_rcgr = 0x5000,
> .hid_width = 5,
next prev parent reply other threads:[~2022-12-27 12:04 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-27 1:32 [RFC PATCH 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-28 20:23 ` Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
2022-12-28 10:30 ` Krzysztof Kozlowski
2022-12-27 1:32 ` [RFC PATCH 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 Dmitry Baryshkov
2022-12-28 10:31 ` Krzysztof Kozlowski
2022-12-28 20:24 ` Dmitry Baryshkov
2022-12-27 1:32 ` [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-12-27 11:48 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Dmitry Baryshkov
2022-12-27 11:49 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-27 11:55 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
2022-12-27 11:58 ` Konrad Dybcio
2022-12-27 12:17 ` Dmitry Baryshkov
2022-12-27 12:19 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-12-27 12:00 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down Dmitry Baryshkov
2022-12-27 12:00 ` Konrad Dybcio [this message]
2022-12-27 1:32 ` [RFC PATCH 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks Dmitry Baryshkov
2022-12-27 12:01 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-27 12:07 ` Konrad Dybcio
2022-12-27 1:32 ` [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Dmitry Baryshkov
2022-12-27 12:08 ` Konrad Dybcio
2022-12-27 12:31 ` Dmitry Baryshkov
2022-12-27 13:04 ` Konrad Dybcio
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