From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8840FC07E85 for ; Fri, 7 Dec 2018 14:26:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C9B320837 for ; Fri, 7 Dec 2018 14:26:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="YV5yhVNj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C9B320837 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-clk-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726034AbeLGO0t (ORCPT ); Fri, 7 Dec 2018 09:26:49 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2869 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726018AbeLGO0t (ORCPT ); Fri, 7 Dec 2018 09:26:49 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 07 Dec 2018 06:26:47 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 07 Dec 2018 06:26:49 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 07 Dec 2018 06:26:49 -0800 Received: from [10.21.132.148] (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 7 Dec 2018 14:26:47 +0000 Subject: Re: [PATCH 07/19] clk: tegra: dfll: support PWM regulator control To: Joseph Lo , Thierry Reding , Peter De Schrijver CC: , , References: <20181204092548.3038-1-josephl@nvidia.com> <20181204092548.3038-8-josephl@nvidia.com> From: Jon Hunter Message-ID: <6cdab503-e463-ddbb-2ce9-035c81da7058@nvidia.com> Date: Fri, 7 Dec 2018 14:26:45 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181204092548.3038-8-josephl@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544192807; bh=gPl1CD0yfdiwDuvQ5CCsCW96W+yZA7YuvqjX2aIXMKw=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=YV5yhVNj5si7qPwTY8WZqk7YQZlBJ6YuVfPWLUhCphTpCMjx8j+ud1DJKPdhin38c 5BA30i7BTMc1vMOYOflfNjjOM543+Hwkb9WEf+6u3vRXBIInRbsEQlOCCPLr3btqbo wIiaO3m6nTySQ7RqKQFJRFFOp4mFYP0d4sGVADblRcIBb/VRUYS/5Mf/4UD14Q3aH0 9cRwNihxmTGGNWpfLyHpONg/O48E2onVjZKeBMYFLCoY6hKP+zpEDtCpXeEHo+nRCH fNXTGph5ntZ0L0JTPIxaEtqtTjnBvtqtPfyjNTKiYSTbk523LHrV8zOi2of5PvCFhi AEmYtliasZg5A== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 04/12/2018 09:25, Joseph Lo wrote: > The DFLL hardware supports two modes (I2C and PWM) for voltage control > when requesting a frequency. In this patch, we introduce PWM mode support. > > To support that, we re-organize the LUT for unifying the table for both > cases of I2C and PWM mode. And generate that based on regulator info. > For the PWM-based regulator, we get this info from DT. And do the same as > the case of I2C LUT, which can help to map the PMIC voltage ID and voltages > that the regulator supported. > > The other parts are the support code for initializing the DFLL hardware > to support PWM mode. Also, the register debugfs file is slightly > reworked to only show the i2c registers when I2C mode is in use. > > Based on the work of Peter De Schrijver . > > Signed-off-by: Joseph Lo > --- > drivers/clk/tegra/clk-dfll.c | 431 ++++++++++++++++++++++++++++++----- > 1 file changed, 368 insertions(+), 63 deletions(-) > > diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c > index 609e363dabf8..c294a2989f31 100644 > --- a/drivers/clk/tegra/clk-dfll.c > +++ b/drivers/clk/tegra/clk-dfll.c > @@ -1,7 +1,7 @@ > /* > * clk-dfll.c - Tegra DFLL clock source common code > * > - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. > + * Copyright (C) 2012-2018 NVIDIA Corporation. All rights reserved. > * > * Aleksandr Frid > * Paul Walmsley > @@ -47,6 +47,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -243,6 +244,12 @@ enum dfll_tune_range { > DFLL_TUNE_LOW = 1, > }; > > + > +enum tegra_dfll_pmu_if { > + TEGRA_DFLL_PMU_I2C = 0, > + TEGRA_DFLL_PMU_PWM = 1, > +}; > + > /** > * struct dfll_rate_req - target DFLL rate request data > * @rate: target frequency, after the postscaling > @@ -294,16 +301,25 @@ struct tegra_dfll { > u32 ci; > u32 cg; > bool cg_scale; > + u32 reg_init_uV; Doesn't this belong under PWM interface? Also being picky I dont' find init_uV very descriptive. Otherwise the change looks fine to me. Cheers Jon -- nvpublic