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Thu, 19 Sep 2024 14:14:15 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 48JEEDbB029992 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Sep 2024 14:14:13 GMT Received: from [10.253.37.179] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 19 Sep 2024 07:14:08 -0700 Message-ID: <6f1118eb-89cf-4fd4-a35d-e8b98b0b7a8d@quicinc.com> Date: Thu, 19 Sep 2024 22:14:06 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/5] Add support for PCIe3 on x1e80100 To: Krishna Chaitanya Chundru , , , , , , , , , , , , , CC: , , , , , , , , , References: <20240913083724.1217691-1-quic_qianyu@quicinc.com> <36bd9f69-e263-08a1-af07-45185ea03671@quicinc.com> Content-Language: en-US From: Qiang Yu In-Reply-To: <36bd9f69-e263-08a1-af07-45185ea03671@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _mdC1IH3zYXwxrLCQBtGo18Z4GNH8Uo0 X-Proofpoint-ORIG-GUID: _mdC1IH3zYXwxrLCQBtGo18Z4GNH8Uo0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 adultscore=0 impostorscore=0 phishscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 mlxscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409190093 On 9/14/2024 11:59 AM, Krishna Chaitanya Chundru wrote: > Hi qiang, > > In next series can you add logic in controller driver > to have new ops for this x1e80100 since this hardware > has smmuv3 support but currently the ops_1_9_0 ops which > is being used has configuring bdf to sid table which will > be not present for this devices. > Sure, bdf2sid map is not supported and required since we use smmuv3 for pcie on x1e80100. Can I add a new ops which is same as ops_1_9_0 basically and only config_sid callback is removed. Or add a new flag to determine if we need to config bdf2sid map like no_l0s. Hi Mani, what do you think about this? Thanks, Qiang > > - Krishna Chaitanya. > > On 9/13/2024 2:07 PM, Qiang Yu wrote: >> This series add support for PCIe3 on x1e80100. >> >> PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP >> PHY configuration compare other PCIe instances on x1e80100. Hence add >> required resource configuration and usage for PCIe3. >> >> v2->v1: >> 1. Squash [PATCH 1/8], [PATCH 2/8],[PATCH 3/8] into one patch and >> make the >>     indentation consistent. >> 2. Put dts patch at the end of the patchset. >> 3. Put dt-binding patch at the first of the patchset. >> 4. Add a new patch where opp-table is added in dt-binding to avoid dtbs >>     checking error. >> 5. Remove GCC_PCIE_3_AUX_CLK, RPMH_CXO_CLK, put in >> TCSR_PCIE_8L_CLKREF_EN >>     as ref. >> 6. Remove lane_broadcasting. >> 7. Add 64 bit bar, Remove GCC_PCIE_3_PIPE_CLK_SRC, >>     GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK is changed to >>     GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK. >> 8. Add Reviewed-by tag. >> 9. Remove [PATCH 7/8], [PATCH 8/8]. >> >> Qiang Yu (5): >>    dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 >>      QMP PCIe PHY Gen4 x8 >>    dt-bindings: PCI: qcom: Add OPP table for X1E80100 >>    phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 >>    clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks >>    arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 >> >>   .../bindings/pci/qcom,pcie-x1e80100.yaml      |   4 + >>   .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |   3 + >>   arch/arm64/boot/dts/qcom/x1e80100.dtsi        | 202 ++++++++++++++++- >>   drivers/clk/qcom/gcc-x1e80100.c               |  10 +- >>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c      | 211 ++++++++++++++++++ >>   .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h    |  25 +++ >>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h |  19 ++ >>   7 files changed, 468 insertions(+), 6 deletions(-) >>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h >>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h >>