Re: [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq support

Konrad Dybcio
2025-03-08T18:18:50Z

On 27.01.2025 10:31 AM, Sricharan R wrote:
> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

subject: you're not enabling support, you're either enabling cpufreq (the
feature), or adding support for it

> Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for
> CPU clock scaling.
>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---

[...]

> + cpu_opp_table: opp-table-cpu {
> + compatible = "operating-points-v2-kryo-cpu";
> + opp-shared;
> + nvmem-cells = <&cpu_speed_bin>;
> +
> + /*
> + * CPU supports two frequencies and the fuse has LValue instead
> + * of limits. As only two frequencies are supported, considering
> + * zero Lvalue as no limit and Lvalue as 1.4GHz limit.
> + * ------------------------------------------------------------
> + * Frequency BIT1 BIT0 opp-supported-hw
> + * 1.4GHz No Limit
> + * ------------------------------------------------------------
> + * 1416000000 1 1 0x3
> + * 1800000000 0 1 0x1
> + * ------------------------------------------------------------
> + */

This is trivially inferred from the nodes below

> +
> + opp-1416000000 {
> + opp-hz = /bits/ 64 <1416000000>;
> + opp-microvolt = <1>;
> + opp-supported-hw = <0x3>;
> + clock-latency-ns = <200000>;
> + };
> +
> + opp-1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <2>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> memory@80000000 {
> device_type = "memory";
> /* We expect the bootloader to fill in the size */
> @@ -151,6 +202,18 @@ soc@0 {
> #size-cells = <2>;
> ranges = <0 0 0 0 0x10 0>;
>
> + qfprom@a6000 {
> + compatible = "qcom,qfprom";
> + reg = <0x0 0xa6000 0x0 0x1000>;

Please pad the address part to 8 hex digits with leading zeroes

Konrad