[PATCH 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq support

Sricharan R
2025-01-27T09:32:10Z

From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for
CPU clock scaling.

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 71 +++++++++++++++++++++++++++
1 file changed, 71 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 577b88cd5172..3c07f7c28c4a 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -7,6 +7,7 @@
*/

#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
#include <dt-bindings/gpio/gpio.h>
@@ -38,6 +39,11 @@ cpu0: cpu@0 {
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;
+
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
@@ -58,6 +64,10 @@ cpu1: cpu@100 {
enable-method = "psci";
reg = <0x100>;
next-level-cache = <&l2_100>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;

l2_100: l2-cache {
compatible = "cache";
@@ -73,6 +83,10 @@ cpu2: cpu@200 {
enable-method = "psci";
reg = <0x200>;
next-level-cache = <&l2_200>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;

l2_200: l2-cache {
compatible = "cache";
@@ -88,6 +102,10 @@ cpu3: cpu@300 {
enable-method = "psci";
reg = <0x300>;
next-level-cache = <&l2_300>;
+ clocks = <&apss_clk APSS_SILVER_CORE_CLK>,
+ <&apss_clk L3_CORE_CLK>;
+ clock-names = "cpu", "l3_core";
+ operating-points-v2 = <&cpu_opp_table>;

l2_300: l2-cache {
compatible = "cache";
@@ -98,6 +116,39 @@ l2_300: l2-cache {
};
};

+ cpu_opp_table: opp-table-cpu {
+ compatible = "operating-points-v2-kryo-cpu";
+ opp-shared;
+ nvmem-cells = <&cpu_speed_bin>;
+
+ /*
+ * CPU supports two frequencies and the fuse has LValue instead
+ * of limits. As only two frequencies are supported, considering
+ * zero Lvalue as no limit and Lvalue as 1.4GHz limit.
+ * ------------------------------------------------------------
+ * Frequency BIT1 BIT0 opp-supported-hw
+ * 1.4GHz No Limit
+ * ------------------------------------------------------------
+ * 1416000000 1 1 0x3
+ * 1800000000 0 1 0x1
+ * ------------------------------------------------------------
+ */
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1>;
+ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <2>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -151,6 +202,18 @@ soc@0 {
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;

+ qfprom@a6000 {
+ compatible = "qcom,qfprom";
+ reg = <0x0 0xa6000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_bin: cpu-speed-bin@234 {
+ reg = <0x234 0x1>;
+ bits = <0 8>;
+ };
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5424-tlmm";
reg = <0 0x01000000 0 0x300000>;
@@ -363,6 +426,14 @@ frame@f42d000 {
};
};

+ apss_clk: apss-clock@fa80000 {
+ compatible = "qcom,ipq5424-apss-clk";
+ reg = <0x0 0x0fa80000 0x0 0x20000>;
+ clocks = <&xo_board>, <&gcc GPLL0>;
+ clock-names = "xo", "gpll0";
+ #clock-cells = <1>;
+ };
+
tmel_qmp: qmp@32090000 {
compatible = "qcom,ipq5424-tmel-qmp", "qcom,tmel-qmp";
reg = <0 0x32090000 0 0x2000>;
--
2.34.1