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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2985c2bf17dsm161875525ad.94.2025.11.17.22.44.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 22:44:32 -0800 (PST) Message-ID: <71e0d879-63ed-49e7-9bfe-c5cd8e0ca8ba@oss.qualcomm.com> Date: Tue, 18 Nov 2025 14:44:22 +0800 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] clk: qcom: Add TCSR clock driver for Kaanapali To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251030-gcc_kaanapali-v2-v2-0-a774a587af6f@oss.qualcomm.com> <20251030-gcc_kaanapali-v2-v2-5-a774a587af6f@oss.qualcomm.com> Content-Language: en-US From: Jingyi Wang In-Reply-To: <20251030-gcc_kaanapali-v2-v2-5-a774a587af6f@oss.qualcomm.com> Content-Type: text/plain; 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> + > +static struct clk_branch tcsr_pcie_0_clkref_en = { > + .halt_reg = 0x0, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x0, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_pcie_0_clkref_en", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + Hi Taniya, Here is a discussion for tcsr in this thread: https://lore.kernel.org/all/01de9616-825b-4fbb-83cf-e0bf91e8cf39@oss.qualcomm.com/ As TCSR_CLKS is a part of tcsr block, we should merge it as one node, the address should be start at 0x01fc0000 instead of 0x01fd5044, so offset need to be added in the tcsrcc reg configuration. Thanks, Jingyi > +static struct clk_branch tcsr_ufs_clkref_en = { > + .halt_reg = 0x10, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x10, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_ufs_clkref_en", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO_PAD, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch tcsr_usb2_clkref_en = { > + .halt_reg = 0x18, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x18, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_usb2_clkref_en", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO_PAD, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch tcsr_usb3_clkref_en = { > + .halt_reg = 0x8, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x8, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "tcsr_usb3_clkref_en", > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_BI_TCXO_PAD, > + }, > + .num_parents = 1, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_regmap *tcsr_cc_kaanapali_clocks[] = { > + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, > + [TCSR_UFS_CLKREF_EN] = &tcsr_ufs_clkref_en.clkr, > + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, > + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, > +}; > + > +static const struct regmap_config tcsr_cc_kaanapali_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x18, > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc tcsr_cc_kaanapali_desc = { > + .config = &tcsr_cc_kaanapali_regmap_config, > + .clks = tcsr_cc_kaanapali_clocks, > + .num_clks = ARRAY_SIZE(tcsr_cc_kaanapali_clocks), > +}; > + > +static const struct of_device_id tcsr_cc_kaanapali_match_table[] = { > + { .compatible = "qcom,kaanapali-tcsr" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, tcsr_cc_kaanapali_match_table); > + > +static int tcsr_cc_kaanapali_probe(struct platform_device *pdev) > +{ > + return qcom_cc_probe(pdev, &tcsr_cc_kaanapali_desc); > +} > + > +static struct platform_driver tcsr_cc_kaanapali_driver = { > + .probe = tcsr_cc_kaanapali_probe, > + .driver = { > + .name = "tcsr_cc-kaanapali", > + .of_match_table = tcsr_cc_kaanapali_match_table, > + }, > +}; > + > +static int __init tcsr_cc_kaanapali_init(void) > +{ > + return platform_driver_register(&tcsr_cc_kaanapali_driver); > +} > +subsys_initcall(tcsr_cc_kaanapali_init); > + > +static void __exit tcsr_cc_kaanapali_exit(void) > +{ > + platform_driver_unregister(&tcsr_cc_kaanapali_driver); > +} > +module_exit(tcsr_cc_kaanapali_exit); > + > +MODULE_DESCRIPTION("QTI TCSR_CC KAANAPALI Driver"); > +MODULE_LICENSE("GPL"); >