Re: [PATCH] clk: qcom: Fix MSM8998 resets

[Jeffrey Hugo <jhugo@codeaurora.org>]

On 12/3/2018 10:52 AM, Stephen Boyd wrote:
> Quoting Jeffrey Hugo (2018-12-03 09:19:20)
>> On 12/3/2018 10:02 AM, Stephen Boyd wrote:
>>> Quoting Jeffrey Hugo (2018-12-03 08:08:46)
>>>> On 12/3/2018 8:55 AM, Bjorn Andersson wrote:
>>>>> On Mon 03 Dec 07:34 PST 2018, Jeffrey Hugo wrote:
>>>>>
>>>>>> The offsets for the defined BCR reset registers does not match the hardware
>>>>>> documentation.  Update the values to match the hardware documentation.
>>>>>>
>>>>>
>>>>> Sorry for not spotting this before.
>>>>>
>>>>>> Fixes: b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
>>>>>> Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
>>>>>> ---
>>>>>>     drivers/clk/qcom/gcc-msm8998.c | 38 +++++++++++++++++++-------------------
>>>>>>     1 file changed, 19 insertions(+), 19 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
>>>>>> index 9f0ae40..01cc555 100644
>>>>>> --- a/drivers/clk/qcom/gcc-msm8998.c
>>>>>> +++ b/drivers/clk/qcom/gcc-msm8998.c
>>>>>> @@ -2742,25 +2742,25 @@ enum {
>>>>>>     };
>>>>>>     
>>>>>>     static const struct qcom_reset_map gcc_msm8998_resets[] = {
>>>>>> -    [GCC_BLSP1_QUP1_BCR] = { 0x102400 },
>>>>>> -    [GCC_BLSP1_QUP2_BCR] = { 0x110592 },
>>>>>> -    [GCC_BLSP1_QUP3_BCR] = { 0x118784 },
>>>>>> -    [GCC_BLSP1_QUP4_BCR] = { 0x126976 },
>>>>>> -    [GCC_BLSP1_QUP5_BCR] = { 0x135168 },
>>>>>> -    [GCC_BLSP1_QUP6_BCR] = { 0x143360 },
>>>>>> -    [GCC_BLSP2_QUP1_BCR] = { 0x155648 },
>>>>>> -    [GCC_BLSP2_QUP2_BCR] = { 0x163840 },
>>>>>> -    [GCC_BLSP2_QUP3_BCR] = { 0x172032 },
>>>>>> -    [GCC_BLSP2_QUP4_BCR] = { 0x180224 },
>>>>>> -    [GCC_BLSP2_QUP5_BCR] = { 0x188416 },
>>>>>> -    [GCC_BLSP2_QUP6_BCR] = { 0x196608 },
>>>>>> -    [GCC_PCIE_0_BCR] = { 0x438272 },
>>>>>> -    [GCC_PDM_BCR] = { 0x208896 },
>>>>>> -    [GCC_SDCC2_BCR] = { 0x81920 },
>>>>>> -    [GCC_SDCC4_BCR] = { 0x90112 },
>>>>>> -    [GCC_TSIF_BCR] = { 0x221184 },
>>>>>> -    [GCC_UFS_BCR] = { 0x479232 },
>>>>>> -    [GCC_USB_30_BCR] = { 0x61440 },
>>>>>> +    [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
>>>>>> +    [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
>>>>>> +    [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
>>>>>> +    [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
>>>>>> +    [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
>>>>>> +    [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
>>>>>> +    [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
>>>>>> +    [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
>>>>>> +    [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
>>>>>> +    [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
>>>>>> +    [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
>>>>>> +    [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
>>>>>> +    [GCC_PCIE_0_BCR] = { 0x6c01c },
>>>>>
>>>>> I find GCC_PCIE_0_BCR at 0x6b000 and then GCC_PCIE_0_PHY_BCR at 0x6c01c.
>>>>
>>>> Doh.  Thanks for the double check.  GCC_PCIE_0_PHY_BCR is not defined in
>>>> include/dt-bindings/clock/qcom,gcc-msm8998.h so I plan to leave it out
>>>> until later.
>>>>
>>>> Expect a v2 shortly.
>>>
>>> Will you add GCC_PCIE0_PHY_BCR shortly so we don't have to add it later
>>> on when it becomes critical?
>>>
>>
>> My plan was to let it sit until it becomes necessary.  I'm working on
>> USB and found that GCC_QUSB2PHY_PRIM_BCR, GCC_USB3_PHY_BCR, and
>> GCC_USB3PHY_PHY_BCR are also missing, so I suspect there are others.
>>
>> Would you prefer I send a follow up that adds the PCIE phy and the USB
>> resets?
> 
> Yes please send a followup patch to add all the possible defines and
> implementations that you can find. It makes future cross-tree merges
> simpler.
> 

Ok, will do.  Will need a bit of time to review the hardware 
documentation to enumerate a comprehensive list.  I'm thinking by the 
end of the week.

-- 
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.