From: Jeffrey Hugo <jhugo@codeaurora.org>
To: Rob Clark <robdclark@gmail.com>,
dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org,
aarch64-laptops@lists.linaro.org, linux-clk@vger.kernel.org,
linux-pm@vger.kernel.org, Rob Clark <robdclark@chromium.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Jordan Crouse <jcrouse@codeaurora.org>,
Abhinav Kumar <abhinavk@codeaurora.org>,
Sibi Sankar <sibis@codeaurora.org>,
Mamta Shukla <mamtashukla555@gmail.com>,
Chandan Uddaraju <chandanu@codeaurora.org>,
Archit Taneja <architt@codeaurora.org>,
Rajesh Yadav <ryadav@codeaurora.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] drm/msm/dsi: get the clocks into OFF state at init
Date: Mon, 1 Jul 2019 12:37:44 -0600 [thread overview]
Message-ID: <75a2921d-bf1a-c4c1-6d9a-122474eface4@codeaurora.org> (raw)
In-Reply-To: <20190630150230.7878-5-robdclark@gmail.com>
On 6/30/2019 9:01 AM, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> Do an extra enable/disable cycle at init, to get the clks into disabled
> state in case bootloader left them enabled.
>
> In case they were already enabled, the clk_prepare_enable() has no real
> effect, other than getting the enable_count/prepare_count into the right
> state so that we can disable clocks in the correct order. This way we
> avoid having stuck clocks when we later want to do a modeset and set the
> clock rates.
>
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 18 +++++++++++++++---
> drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 1 +
> 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> index aabab6311043..d0172d8db882 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> @@ -354,6 +354,7 @@ static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
> if (rc)
> pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
> pll->id, status);
> +rc = 0; // HACK, this will fail if PLL already running..
Umm, why? Is this intentional?
--
Jeffrey Hugo
Qualcomm Datacenter Technologies as an affiliate of Qualcomm
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
next prev parent reply other threads:[~2019-07-01 18:37 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-30 15:01 [PATCH 0/5] drm+clk+genpd: support for bootloader enabled display Rob Clark
2019-06-30 15:01 ` [PATCH 1/5] clk: inherit clocks enabled by bootloader Rob Clark
2019-07-01 18:02 ` [Freedreno] " Jeffrey Hugo
2019-07-01 18:25 ` Eric Anholt
2019-07-01 19:05 ` Rob Clark
2019-06-30 15:01 ` [PATCH 2/5] genpd/gdsc: inherit display powerdomain from bootloader Rob Clark
2019-07-01 18:08 ` [Freedreno] " Jeffrey Hugo
2019-06-30 15:01 ` [PATCH 3/5] drm/msm/dsi: split clk rate setting and enable Rob Clark
2019-07-01 18:32 ` [Freedreno] " Jeffrey Hugo
2019-06-30 15:01 ` [PATCH 4/5] drm/msm/dsi: get the clocks into OFF state at init Rob Clark
2019-07-01 18:37 ` Jeffrey Hugo [this message]
2019-07-01 18:58 ` Rob Clark
2019-07-01 19:07 ` Jeffrey Hugo
2019-07-01 19:34 ` Rob Clark
2019-07-02 13:53 ` Rob Clark
2019-06-30 15:01 ` [PATCH 5/5] drm/bridge: ti-sn65dsi86: support booloader enabled display Rob Clark
2019-07-01 18:39 ` Jeffrey Hugo
2019-07-02 15:20 ` Laurent Pinchart
2019-07-02 15:38 ` Rob Clark
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