From: "André Draszik" <andre.draszik@linaro.org>
To: Tudor Ambarus <tudor.ambarus@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Peter Griffin <peter.griffin@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Sylwester Nawrocki <s.nawrocki@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
willmcvicker@google.com, kernel-team@android.com
Subject: Re: [PATCH v5 4/5] clk: samsung: add Exynos ACPM clock driver
Date: Wed, 24 Sep 2025 17:00:31 +0100 [thread overview]
Message-ID: <798600a43825818bcf828da7060f38105f7f3225.camel@linaro.org> (raw)
In-Reply-To: <20250924-acpm-clk-v5-4-4cca1fadd00d@linaro.org>
Hi Tudor,
On Wed, 2025-09-24 at 15:11 +0000, Tudor Ambarus wrote:
> Add the Exynos ACPM clock driver. It provides support for clocks that
> are controlled by firmware that implements the ACPM interface.
[...]
> diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..9e8354168a63b1427c2f3faf15e4e7955e924dc8
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-acpm.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Samsung Exynos ACPM protocol based clock driver.
> + *
> + * Copyright 2025 Linaro Ltd.
> + */
> +
> +#include <linux/array_size.h>
> +#include <linux/clk-provider.h>
> +#include <linux/container_of.h>
> +#include <linux/device/devres.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/firmware/samsung/exynos-acpm-protocol.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +
> +struct acpm_clk {
> + u32 id;
> + struct clk_hw hw;
> + unsigned int mbox_chan_id;
> + const struct acpm_handle *handle;
> +};
> +
> +struct acpm_clk_variant {
> + const char *name;
> +};
> +
> +struct acpm_clk_driver_data {
> + const struct acpm_clk_variant *clks;
> + unsigned int nr_clks;
> + unsigned int mbox_chan_id;
> +};
> +
> +#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw)
> +
> +#define ACPM_CLK(cname) \
> + { \
> + .name = cname, \
> + }
> +
> +static const struct acpm_clk_variant gs101_acpm_clks[] = {
> + ACPM_CLK("mif"),
> + ACPM_CLK("int"),
> + ACPM_CLK("cpucl0"),
> + ACPM_CLK("cpucl1"),
> + ACPM_CLK("cpucl2"),
> + ACPM_CLK("g3d"),
> + ACPM_CLK("g3dl2"),
> + ACPM_CLK("tpu"),
> + ACPM_CLK("intcam"),
> + ACPM_CLK("tnr"),
> + ACPM_CLK("cam"),
> + ACPM_CLK("mfc"),
> + ACPM_CLK("disp"),
> + ACPM_CLK("b0"),
The last one should be 'bo' (bigocean), not b0.
Cheers,
Andre'
next prev parent reply other threads:[~2025-09-24 16:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 15:10 [PATCH v5 0/5] exynos-acpm: add DVFS protocol and clock driver Tudor Ambarus
2025-09-24 15:11 ` [PATCH v5 1/5] dt-bindings: firmware: google,gs101-acpm-ipc: add ACPM clocks Tudor Ambarus
2025-09-24 15:11 ` [PATCH v5 2/5] firmware: exynos-acpm: add DVFS protocol Tudor Ambarus
2025-09-24 15:24 ` André Draszik
2025-09-26 9:15 ` Tudor Ambarus
2025-09-24 15:11 ` [PATCH v5 3/5] firmware: exynos-acpm: register ACPM clocks pdev Tudor Ambarus
2025-09-24 15:11 ` [PATCH v5 4/5] clk: samsung: add Exynos ACPM clock driver Tudor Ambarus
2025-09-24 16:00 ` André Draszik [this message]
2025-09-26 9:16 ` Tudor Ambarus
2025-09-24 15:11 ` [PATCH v5 5/5] arm64: defconfig: enable Exynos ACPM clocks Tudor Ambarus
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