From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72759C433F5 for ; Tue, 19 Apr 2022 06:38:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348936AbiDSGle (ORCPT ); Tue, 19 Apr 2022 02:41:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348944AbiDSGlc (ORCPT ); Tue, 19 Apr 2022 02:41:32 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D40C42ED65; Mon, 18 Apr 2022 23:38:50 -0700 (PDT) X-UUID: 76d3548de5da4a5aadd8b08a5b9e2abe-20220419 X-UUID: 76d3548de5da4a5aadd8b08a5b9e2abe-20220419 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1289611600; Tue, 19 Apr 2022 14:38:42 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Tue, 19 Apr 2022 14:38:41 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 19 Apr 2022 14:38:40 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 19 Apr 2022 14:38:40 +0800 Message-ID: <7e6ca7055ad6c236cb43b73c0b32a435033bb37d.camel@mediatek.com> Subject: Re: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting register From: Rex-BC Chen To: Chen-Yu Tsai CC: , , , , , , , , , , , , , Date: Tue, 19 Apr 2022 14:38:40 +0800 In-Reply-To: References: <20220418132154.7401-1-rex-bc.chen@mediatek.com> <20220418132154.7401-2-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On Tue, 2022-04-19 at 13:48 +0800, Chen-Yu Tsai wrote: > Hi, > > On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen > wrote: > > > > The subject could be written as "Fix written reset bit offset" to > make it > more specific. Hello ChenYu, I will update the topic in next version. Thanks for your suggestion. BRs, Rex > > > Original assert/deassert bit is BIT(0), but it's more resonable to > > modify > > them to BIT(id % 32) which is based on id. > > > > This patch will not influence any previous driver because the reset > > is > > only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is > > 0. > > > > Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") > > Signed-off-by: Rex-BC Chen > > Otherwise, > > Reviewed-by: Chen-Yu Tsai