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Thu, 04 Apr 2024 07:04:41 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43474duD023310 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 4 Apr 2024 07:04:39 GMT Received: from [10.218.10.146] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 4 Apr 2024 00:04:34 -0700 Message-ID: <7fd8c4ab-22a2-2d0c-2257-14441ae79c29@quicinc.com> Date: Thu, 4 Apr 2024 12:34:31 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 2/7] dt-bindings: clock: qcom: Add DISPCC clocks for SM4450 Content-Language: en-US To: Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Vladimir Zapolskiy CC: , , , Taniya Das , "Jagadeesh Kona" , Imran Shaik , "Satya Priya Kakitapalli" References: <20240330182817.3272224-1-quic_ajipan@quicinc.com> <20240330182817.3272224-3-quic_ajipan@quicinc.com> From: Ajit Pandey In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oukr3H6ohs_ZSi4B6sbxB-AYzoBb_50o X-Proofpoint-ORIG-GUID: oukr3H6ohs_ZSi4B6sbxB-AYzoBb_50o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-04_02,2024-04-04_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 malwarescore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404040045 On 3/31/2024 1:47 PM, Krzysztof Kozlowski wrote: > On 30/03/2024 19:28, Ajit Pandey wrote: >> Add support for qcom display clock controller bindings >> for SM4450 platform. > > You cannot add support for a binding. Either you add a binding or not. > Please look at git history for inspiration. > Thanks, will update commit msg in next series >> >> Signed-off-by: Ajit Pandey > > >> + >> + clocks: >> + items: >> + - description: Board XO source >> + - description: Board active XO source >> + - description: Display AHB clock source from GCC >> + - description: sleep clock source >> + - description: Byte clock from DSI PHY0 >> + - description: Pixel clock from DSI PHY0 >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#reset-cells': >> + const: 1 >> + >> + '#power-domain-cells': >> + const: 1 > > No power-domain? This looks incomplete. > > Best regards, > Krzysztof > SM4450 doesn't support MMCX hence power-domain isn't required -- Thanks, and Regards Ajit