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[71.197.186.152]) by smtp.googlemail.com with ESMTPSA id o14sm2675345pjp.29.2019.06.28.11.13.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Jun 2019 11:13:09 -0700 (PDT) From: Kevin Hilman To: Neil Armstrong , jbrunet@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, martin.blumenstingl@googlemail.com, linux-gpio@vger.kernel.org, Neil Armstrong Subject: Re: [RFC/RFT v2 00/14] arm64: g12a: add support for DVFS In-Reply-To: <20190626090632.7540-1-narmstrong@baylibre.com> References: <20190626090632.7540-1-narmstrong@baylibre.com> Date: Fri, 28 Jun 2019 11:13:08 -0700 Message-ID: <7hblyhr32j.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Neil Armstrong writes: > The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : > cpu_clk / cpub_clk > | \- cpu_clk_dyn > | | \- cpu_clk_premux0 > | | |- cpu_clk_postmux0 > | | | |- cpu_clk_dyn0_div > | | | \- xtal/fclk_div2/fclk_div3 > | | \- xtal/fclk_div2/fclk_div3 > | \- cpu_clk_premux1 > | |- cpu_clk_postmux1 > | | |- cpu_clk_dyn1_div > | | \- xtal/fclk_div2/fclk_div3 > | \- xtal/fclk_div2/fclk_div3 > \ sys_pll / sys1_pll > > This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, > cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of > the CPU clock in a safe way as recommended by the vendor Documentation > and reference code. > > This patchset : > - introduces needed core and meson clk changes > - adds support for the G12B second cluster clock measurer ids > - protects clock measurer from cooncurent measures > - adds the clock notifiers > - moves the G12A DT to a common g12a-common dtsi > - adds the G12A and G12B OPPs > - enables DVFS on all supported boards > > Dependencies: > - PWM AO input order fix at [1] > - PWM enhancements from Martin at [2] > > Changes since RFT/RFC v1 at [3]: > - Added EXPORT_SYMBOL_GPL() to clk_hw_set_parent > - Added missing static to g12b_cpub_clk_mux0_div_ops and g12a_cpu_clk_mux_nb > - Simplified g12a_cpu_clk_mux_notifier_cb() without switch/case > - Fixed typo in "this the current path" in g12a.c > - Fixed G12B dtsi by adding back the sdio quirk > - Fixed G12A dtsi unwanted sdio quirk removal > - Fixed various checkpatch errors > > [1] https://patchwork.kernel.org/patch/11006835/ > [2] https://patchwork.kernel.org/patch/11006835/ > [3] https://patchwork.kernel.org/cover/11006929/ > > Neil Armstrong (14): > pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmux > clk: core: introduce clk_hw_set_parent() > clk: meson: regmap: export regmap_div ops functions > clk: meson: eeclk: add setup callback > soc: amlogic: meson-clk-measure: protect measure with a mutex > soc: amlogic: meson-clk-measure: add G12B second cluster cpu clk > clk: meson: g12a: add notifiers to handle cpu clock change > clk: meson: g12a: expose CPUB clock ID for G12B > arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi > arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux > arm64: dts: meson-g12a: add cpus OPP table > arm64: dts: meson-g12a: enable DVFS on G12A boards > arm64: dts: meson-g12b: add cpus OPP tables > arm64: dts: meson-g12b-odroid-n2: enable DVFS The DT files don't apply cleanly to my tree (v5.3/dt64 branch). Could you rebase: Then I can put into my testing branch, which gets included in 'integ' and it will be easier for others to test. Kevin