From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB2FC1EA90; Thu, 8 Aug 2024 14:38:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723127899; cv=none; b=haAMG5QrUg8ogH4QOGCZAV9fpPJqVI2bXndzoQo4T7SxP/ILJiBl7zJqzPt8qu7HUxSWEPBJvZpVBlzdkn6qFOF6aVHVoOx/th0IgVelHK9dVHDeMFiH1haxCKONmpb2PjBZVKCFWu2ricxKg5Ff9xdsSE8k+KCHMXXZci9GEOc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723127899; c=relaxed/simple; bh=hSjeiqnr5aAwzBd9Sn/yugh4BM6IEWpBe7Pwe72BkFo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=BlG2p2JoCYQfhht+wovRdq1fq99l/W2yD3lkrfReIxZJXitfHG2sc6zCtmq0IxVA9v0Zi3fW7VTxvgTjtZKji24GQn0tRe9zJlmwAq4act2jyj61Z22dB8cGB6TVfU7wZzh2F09KgpgeQLj8IAaMITokMfoWZK0seM49n3/mqBo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ll/vCCmj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ll/vCCmj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7BA0CC32782; Thu, 8 Aug 2024 14:38:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723127898; bh=hSjeiqnr5aAwzBd9Sn/yugh4BM6IEWpBe7Pwe72BkFo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ll/vCCmjpYcq2iE4+J9AQl5/DG+FrNlA6rrsxAIk9EzGG/b272cMSGh56Q48mRu7t QSVQA6Qt6D6JXXzBqtRXg0uQU6suADxza38PIavs9PVeH2wuKX94sIhpIl1hsbwr6p Io51hkuPaLaamLaCo4pwiwVivzfPG1y4P+UZEgHdlSbC3P1I4SylnkyG0rr29J++y+ nDZgTOMHzYF3+l+0EnlnfpN/OpeirXggTIHQTq76qQpvsITXzXzQvuQizhpPQm9DRO 3M2XAmehhEY2EoLwasjF5GhtWmyydYZSiOY2acDcysVAfZu2B4HLC4j+l4fCy1up2o QsuBzgw9lPD/Q== Message-ID: <81524fee-c32c-405b-b63b-d048dde6ae33@kernel.org> Date: Thu, 8 Aug 2024 16:38:11 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: clock: qcom: Add common PLL clock controller for IPQ SoC To: Luo Jie , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_kkumarcs@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com References: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> <20240808-qcom_ipq_cmnpll-v1-1-b0631dcbf785@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/08/2024 16:03, Luo Jie wrote: > The common PLL controller provides clocks to networking hardware > blocks on Qualcomm IPQ SoC. It receives input clock from the on-chip > Wi-Fi, and produces output clocks at fixed rates. These output rates > are predetermined, and are unrelated to the input clock rate. The > output clocks are supplied to the Ethernet hardware such as PPE > (packet process engine) and the externally connected switch or PHY > device. > > The common PLL driver is initially being supported for IPQ9574 SoC. Drop references to driver and explain the hardware. Above with the usage of "common" looks like this is all for some common driver, not for particular hardware. > > Signed-off-by: Luo Jie > --- > .../bindings/clock/qcom,ipq-cmn-pll.yaml | 87 ++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq-cmn-pll.yaml > new file mode 100644 > index 000000000000..c45b3a201751 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq-cmn-pll.yaml Use compatible as filename. > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,ipq-cmn-pll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Common PLL Clock Controller on IPQ SoC > + > +maintainers: > + - Bjorn Andersson > + - Luo Jie > + > +description: > + The common PLL clock controller expects a reference input clock. > + This reference clock is from the on-board Wi-Fi. The CMN PLL > + supplies a number of fixed rate output clocks to the Ethernet > + devices including PPE (packet process engine) and the connected > + switch or PHY device. > + > +properties: > + compatible: > + enum: > + - qcom,ipq9574-cmn-pll > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: The reference clock, the supported clock rates include > + 25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ. > + - description: The AHB clock > + - description: The SYS clock > + description: > + The reference clock is the source clock of CMN PLL, which is from the > + Wi-Fi. The AHB and SYS clocks must be enabled to access common PLL > + clock registers. > + > + clock-names: > + items: > + - const: ref > + - const: ahb > + - const: sys > + > + clock-output-names: > + items: > + - const: ppe-353mhz > + - const: eth0-50mhz > + - const: eth1-50mhz > + - const: eth2-50mhz > + - const: eth-25mhz Drop entire property. If the names are fixed, what's the point of having it in DTS? There is no. Best regards, Krzysztof