Re: [PATCH 2/4] clk: qcom: Add common PLL clock controller driver for IPQ SoC

kernel test robot
2024-08-10T23:54:13Z

Hi Luo,

kernel test robot noticed the following build errors:

[auto build test ERROR on 222a3380f92b8791d4eeedf7cd750513ff428adf]

url: https://github.com/intel-lab-lkp/linux/commits/Luo-Jie/dt-bindings-clock-qcom-Add-common-PLL-clock-controller-for-IPQ-SoC/20240808-221059
base: 222a3380f92b8791d4eeedf7cd750513ff428adf
patch link: https://lore.kernel.org/r/20240808-qcom_ipq_cmnpll-v1-2-b0631dcbf785%40quicinc.com
patch subject: [PATCH 2/4] clk: qcom: Add common PLL clock controller driver for IPQ SoC
config: m68k-allmodconfig (https://download.01.org/0day-ci/archive/20240811/202408110756.rSXn1ZRu-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240811/202408110756.rSXn1ZRu-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408110756.rSXn1ZRu-lkp@intel.com/

All errors (new ones prefixed by >>):

drivers/clk/qcom/clk-ipq-cmn-pll.c: In function 'ipq_cmn_pll_config':
>> drivers/clk/qcom/clk-ipq-cmn-pll.c:96:24: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
96 | val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
| ^~~~~~~~~~

vim +/FIELD_PREP +96 drivers/clk/qcom/clk-ipq-cmn-pll.c

77
78 static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
79 {
80 void __iomem *base;
81 u32 val;
82
83 base = devm_of_iomap(dev, dev->of_node, 0, NULL);
84 if (IS_ERR(base))
85 return PTR_ERR(base);
86
87 val = readl(base + CMN_PLL_REFCLK_CONFIG);
88 val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
89
90 /*
91 * Configure the reference input clock selection as per the given rate.
92 * The output clock rates are always of fixed value.
93 */
94 switch (parent_rate) {
95 case 25000000:
> 96 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3);
97 break;
98 case 31250000:
99 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4);
100 break;
101 case 40000000:
102 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6);
103 break;
104 case 48000000:
105 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
106 break;
107 case 50000000:
108 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8);
109 break;
110 case 96000000:
111 val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
112 val &= ~CMN_PLL_REFCLK_DIV;
113 val |= FIELD_PREP(CMN_PLL_REFCLK_DIV, 2);
114 break;
115 default:
116 return -EINVAL;
117 }
118
119 writel(val, base + CMN_PLL_REFCLK_CONFIG);
120
121 /* Update the source clock rate selection. Only 96 MHZ uses 0. */
122 val = readl(base + CMN_PLL_REFCLK_SRC_SELECTION);
123 val &= ~CMN_PLL_REFCLK_SRC_DIV;
124 if (parent_rate != 96000000)
125 val |= FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 1);
126
127 writel(val, base + CMN_PLL_REFCLK_SRC_SELECTION);
128
129 /*
130 * Reset the common PLL block by asserting/de-asserting for 100 ms
131 * each, to ensure the updated configurations take effect.
132 */
133 val = readl(base + CMN_PLL_POWER_ON_AND_RESET);
134 val &= ~CMN_ANA_EN_SW_RSTN;
135 writel(val, base);
136 msleep(100);
137
138 val |= CMN_ANA_EN_SW_RSTN;
139 writel(val, base + CMN_PLL_POWER_ON_AND_RESET);
140 msleep(100);
141
142 return 0;
143 }
144

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