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Sat, 10 Jan 2026 07:03:22 -0800 (PST) Received: from [192.168.50.4] ([82.78.167.31]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507bf66214sm12929650a12.27.2026.01.10.07.03.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Jan 2026 07:03:21 -0800 (PST) Message-ID: <81e9c0ea-ca06-4cb9-8f5f-08fec370812b@tuxon.dev> Date: Sat, 10 Jan 2026 17:03:20 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 11/31] clk: at91: clk-usb: add support for clk_parent_data To: Ryan.Wanner@microchip.com, mturquette@baylibre.com, sboyd@kernel.org, alexandre.belloni@bootlin.com, Nicolas.Ferre@microchip.com Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Varshini.Rajendran@microchip.com References: <6979b3734462c97381159f3968a3f22b6193e04d.1758226719.git.Ryan.Wanner@microchip.com> <27aab227-01e3-4074-8aab-38623b4d9808@tuxon.dev> <14ea374c-2889-4bc5-b0c9-fb5b5498593e@microchip.com> <9b97b3b8-9e46-4482-8420-ebabe00254fe@microchip.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <9b97b3b8-9e46-4482-8420-ebabe00254fe@microchip.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, Ryan, Sorry for the late reply, I was off for a while. On 1/5/26 19:58, Ryan.Wanner@microchip.com wrote: > On 12/23/25 07:00, claudiu beznea wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the content is safe >> >> On 12/18/25 18:23, Ryan.Wanner@microchip.com wrote: >>> On 10/20/25 12:17, Claudiu Beznea wrote: >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you >>>> know the content is safe >>>> >>>> Hi, Ryan, >>>> >>>> On 9/19/25 00:15, Ryan.Wanner@microchip.com wrote: >>>>> From: Claudiu Beznea >>>>> >>>>> Add support for clk_parent_data in usb clock driver. >>>>> >>>>> All the SoC based drivers that rely on clk-usb were adapted >>>>> to the new API change. The switch itself for SoCs will be done >>>>> in subsequent patches. >>>>> >>>>> Remove the use of __clk_get_hw() for the slow clocks. >>>>> >>>>> Signed-off-by: Claudiu Beznea >>>>> [ryan.wanner@microchip: Add SAMA7D65 and SAM9X75 SoCs to the changes. >>>>> Change how the main_xtal and slcks are initialized so they match the >>>>> parent_data API] >>>>> Signed-off-by: Ryan Wanner >>>>> --- >>>>>   drivers/clk/at91/at91rm9200.c  |  2 +- >>>>>   drivers/clk/at91/at91sam9260.c |  2 +- >>>>>   drivers/clk/at91/at91sam9g45.c |  2 +- >>>>>   drivers/clk/at91/at91sam9n12.c |  2 +- >>>>>   drivers/clk/at91/at91sam9x5.c  |  2 +- >>>>>   drivers/clk/at91/clk-usb.c     | 41 +++++++++++++++++++++ >>>>> +------------ >>>>>   drivers/clk/at91/dt-compat.c   |  6 ++--- >>>>>   drivers/clk/at91/pmc.h         | 11 +++++---- >>>>>   drivers/clk/at91/sam9x60.c     |  2 +- >>>>>   drivers/clk/at91/sam9x7.c      | 21 +++++++++-------- >>>>>   drivers/clk/at91/sama5d2.c     |  2 +- >>>>>   drivers/clk/at91/sama5d3.c     |  2 +- >>>>>   drivers/clk/at91/sama5d4.c     |  2 +- >>>>>   drivers/clk/at91/sama7d65.c    | 24 +++++++++++--------- >>>>>   14 files changed, 72 insertions(+), 49 deletions(-) >>>>> >>>> >>>> [ ... ] >>>> >>>>> @@ -882,10 +885,10 @@ static void __init sam9x7_pmc_setup(struct >>>>> device_node *np) >>>>> >>>>>        sam9x7_pmc->chws[PMC_MCK] = hw; >>>>> >>>>> -     parent_names[0] = "plla_divpmcck"; >>>>> -     parent_names[1] = "upll_divpmcck"; >>>>> -     parent_names[2] = "main_osc"; >>>>> -     usbck_hw = sam9x60_clk_register_usb(regmap, "usbck", >>>>> parent_names, 3); >>>>> +     parent_data[0] = AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA] >>>>> [PLL_COMPID_DIV0].hw); >>>>> +     parent_data[1] = AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL] >>>>> [PLL_COMPID_DIV0].hw); >>>>> +     parent_data[2] = AT91_CLK_PD_HW(main_osc_hw); >>>>> +     usbck_hw = sam9x60_clk_register_usb(regmap, "usbck", NULL, >>>>> parent_data, 3); >>>> >>>> sam9x60_clk_register_usb() could be converted to use parent_hws >>>> member of >>>> struct clk_init_data instead of parent_data. >>> >>> So this would mean that I would pass in an array of the plls as >>> parent_hws, and use that to load the clk_init_data struct instead of >>> filling the array of parent_data as it is changed to in this patch set? >>> >>> And this would be functionally the same since parent_data points to >>> clk_hw?> >>> >> >> It should be something like: > > I see, I guess my question is why the usbclk system only? Is it just due > to how little parents there are for the usbclk? Or is it because this is > the only clock that only uses clk_hw for all of its parents? Because this is the only clock that uses clk_hw for all of its parents. Thank you, Claudiu