Re: [PATCH v6 4/4] clk: qcom: add clock controller driver for qca8386/qca8084

Jie Luo
2023-09-15T10:00:41Z

On 9/15/2023 12:30 AM, Stephen Boyd wrote:
> Quoting Jie Luo (2023-09-12 20:27:25)
>>
>>
>> On 9/13/2023 1:18 AM, Stephen Boyd wrote:
>>> Quoting Jie Luo (2023-09-12 05:07:02)
>>>>
>>>> and freq_tbl are necessary to this clock.
>>>
>>> I still don't see why the freq_tbl is necessary.
>>
>> Hi Stephen,
>> For clk_rcg2_ops, freq_tbl is used to find the closest rate to decided
>> the parent clock, the configuration of clock source and clock divider
>> are saved in the freq_tbl to configure the RCG hardware register, the
>> mapping of parent clock and hardware register value is decided by the
>> freq_tbl for the RCG clock.
>
> The divider is always 1. The frequency is the frequency of the parent.
> The two pieces of information are already known without the frequency
> table. Why is it needed?

Hi Stephen,
For mac0 and mac5 RCG clock, it is true with divider 1, since these two
MACs are connected with CPU port, which is always the fix link speed,
the clock rate is always 312.5M or 125M, in this case with multiple
parent clocks and divider 1, it seems there is no special RCG clock ops
for it currently, so we leverage the clock ops clk_rcg2_ops.

For other MACs(1-4), which are connected with physical port, the link
speed is dynamically changed, and the divider is different for the
different link speed, such as the mac1 clock freq table as below.

static const struct freq_tbl ftbl_nss_cc_mac1_tx_clk_src[] = {

F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0),

F(25000000, P_UNIPHY1_RX312P5M, 12.5, 0, 0),

F(50000000, P_XO, 1, 0, 0),

F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0),

F(125000000, P_UNIPHY1_RX312P5M, 2.5, 0, 0),

F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0),

F(312500000, P_UNIPHY1_RX312P5M, 1, 0, 0),

{ }

};

Thanks,
Jie.