Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

Devi Priya
2023-01-13T13:33:47Z

On 1/11/2023 3:09 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Add device tree binding documentation details for ipq9574
>> pinctrl driver
>>
>
> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> prefix is already stating that these are bindings.
Sure, okay
>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>> .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml | 129 ++++++++++++++++++
>> 1 file changed, 129 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>> new file mode 100644
>> index 000000000000..f9cb457bc18d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>> @@ -0,0 +1,129 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
>> +
>> +maintainers:
>> + - Anusha <quic_anusha@quicinc.com>
>> +
>> +description: |
>> + This binding describes the Top Level Mode Multiplexer block found in the
>> + IPQ9574 platform.
>
> No, please rebase on recent changes. You started your work on some old
> bindings so your binding likely includes all issues we fixed.
Sure, will do
>
>> +
>> +allOf:
>> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: qcom,ipq9574-tlmm
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + interrupts: true
>> + interrupt-controller: true
>> + "#interrupt-cells": true
>> + gpio-controller: true
>> + gpio-reserved-ranges: true
>> + "#gpio-cells": true
>> + gpio-ranges: true
>> + wakeup-parent: true
>
> Missing gpio-line-names and constraints for ranges. Look at other bindings.
Okay
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +patternProperties:
>> + "-state$":
>> + oneOf:
>> + - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
>> + - patternProperties:
>> + "-pins$":
>> + $ref: "#/$defs/qcom-ipq9574-tlmm-state"
>> + additionalProperties: false
>> +
>> +$defs:
>> + qcom-ipq9574-tlmm-state:
>> + type: object
>> + description:
>> + Pinctrl node's client devices use subnodes for desired pin configuration.
>> + Client device subnodes use below standard properties.
>> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
>> +
>> + properties:
>> + pins:
>> + description:
>> + List of gpio pins affected by the properties specified in this
>> + subnode.
>> + items:
>> + oneOf:
>> + - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>> + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>> + sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>> + qdsd_data3 ]
>
> These are ordered by name.
The enum values seem to be ordered alphabetically.
could you please help us understand the ordering?
>
>> + minItems: 1
>> + maxItems: 8
>> +
>> + function:
>> + description:
>> + Specify the alternative function to be configured for the specified
>> + pins.
>> +
>> + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
>> + audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
>> + blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
>> + blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
>> + blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
>> + cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
>> + gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
>> + mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
>> + pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
>> + prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
>> + pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
>> + pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
>> + pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
>> + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
>> + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
>> + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
>> + dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
>> + rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
>> + wci20, wci21, wsa_swrm, audio_pdm0 ]
>
> These too
>
>> +
>> + bias-disable: true
>> + bias-pull-down: true
>> + bias-pull-up: true
>> + drive-strength: true
>> + input-enable: true
>> + output-high: true
>> + output-low: true
>> +
>> + required:
>> + - pins
>> +
>> + additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + tlmm: pinctrl@1000000 {
>> + compatible = "qcom,ipq9574-tlmm";
>> + reg = <0x01000000 0x300000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 65>;
>> +
>> + uart2-state {
>> + pins = "gpio34", "gpio35";
>
> Wrong indentation.
Okay
>
>> + function = "blsp2_uart";
>> + drive-strength = <8>;
>> + bias-pull-down;
>> + };
>> + };
>
> Best regards,
> Krzysztof
>

Best Regards,
Devi Priya