Re: [PATCH RESEND v3 3/6] include: fpga: adi-axi-common: add new helper macros

["Nuno Sá" <noname.nuno@gmail.com>]

On Thu, 2025-04-24 at 18:16 +0800, Xu Yilun wrote:
> On Mon, Apr 21, 2025 at 03:58:04PM +0100, Nuno Sá via B4 Relay wrote:
> > From: Nuno Sá <nuno.sa@analog.com>
> > 
> > Add new helper macros and enums to help identifying the platform and some
> > characteristics of it at runtime.
> > 
> > Signed-off-by: Nuno Sá <nuno.sa@analog.com>
> > ---
> >  include/linux/fpga/adi-axi-common.h | 35
> > +++++++++++++++++++++++++++++++++++
> 
> I'm wondering why these definitions (including existing ones) are in
> fpga directory. They are not specific for any fpga_manager driver. I
> suggest move the whole file out of fpga/
> 

Just placed them in here because the header already existed in here... If
acceptable, I have not problems in moving this file to include/linux.

- Nuno Sá

> Thanks,
> Yilun
> 
> >  1 file changed, 35 insertions(+)
> > 
> > diff --git a/include/linux/fpga/adi-axi-common.h b/include/linux/fpga/adi-
> > axi-common.h
> > index
> > 141ac3f251e6f256526812b9d55cd440a2a46e76..a832ef9b37473ca339a2a2ff8a4a5716d4
> > 28fd29 100644
> > --- a/include/linux/fpga/adi-axi-common.h
> > +++ b/include/linux/fpga/adi-axi-common.h
> > @@ -12,6 +12,8 @@
> >  #define ADI_AXI_COMMON_H_
> >  
> >  #define ADI_AXI_REG_VERSION			0x0000
> > +#define ADI_AXI_REG_FPGA_INFO			0x001C
> > +#define ADI_AXI_REG_FPGA_VOLTAGE		0x0140
> >  
> >  #define ADI_AXI_PCORE_VER(major, minor, patch)	\
> >  	(((major) << 16) | ((minor) << 8) | (patch))
> > @@ -20,4 +22,37 @@
> >  #define ADI_AXI_PCORE_VER_MINOR(version)	(((version) >> 8) & 0xff)
> >  #define ADI_AXI_PCORE_VER_PATCH(version)	((version) & 0xff)
> >  
> > +#define ADI_AXI_INFO_FPGA_TECH(info)            (((info) >> 24) & 0xff)
> > +#define ADI_AXI_INFO_FPGA_FAMILY(info)          (((info) >> 16) & 0xff)
> > +#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info)     (((info) >> 8) & 0xff)
> > +#define ADI_AXI_INFO_FPGA_VOLTAGE(val)          ((val) & 0xffff)
> > +
> > +enum adi_axi_fpga_technology {
> > +	ADI_AXI_FPGA_TECH_UNKNOWN = 0,
> > +	ADI_AXI_FPGA_TECH_SERIES7,
> > +	ADI_AXI_FPGA_TECH_ULTRASCALE,
> > +	ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS,
> > +};
> > +
> > +enum adi_axi_fpga_family {
> > +	ADI_AXI_FPGA_FAMILY_UNKNOWN = 0,
> > +	ADI_AXI_FPGA_FAMILY_ARTIX,
> > +	ADI_AXI_FPGA_FAMILY_KINTEX,
> > +	ADI_AXI_FPGA_FAMILY_VIRTEX,
> > +	ADI_AXI_FPGA_FAMILY_ZYNQ,
> > +};
> > +
> > +enum adi_axi_fpga_speed_grade {
> > +	ADI_AXI_FPGA_SPEED_UNKNOWN      = 0,
> > +	ADI_AXI_FPGA_SPEED_1    = 10,
> > +	ADI_AXI_FPGA_SPEED_1L   = 11,
> > +	ADI_AXI_FPGA_SPEED_1H   = 12,
> > +	ADI_AXI_FPGA_SPEED_1HV  = 13,
> > +	ADI_AXI_FPGA_SPEED_1LV  = 14,
> > +	ADI_AXI_FPGA_SPEED_2    = 20,
> > +	ADI_AXI_FPGA_SPEED_2L   = 21,
> > +	ADI_AXI_FPGA_SPEED_2LV  = 22,
> > +	ADI_AXI_FPGA_SPEED_3    = 30,
> > +};
> > +
> >  #endif /* ADI_AXI_COMMON_H_ */
> > 
> > -- 
> > 2.49.0
> > 
> > 
> >