From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5E181DEFE6; Mon, 23 Jun 2025 09:49:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750672143; cv=none; b=S0Ev0KWryRxTSqc+OCtuZxml2Tedlyix5vJWPxrfpb2EaVWk4Yy+DwuLT5bpOPIhj7pLcHy5AMdgv1oBNZhCUdhaulKP+UbByiZUrEVb/0j22CdWKWIGjs6lFWHXq5oJDcw1YQ3dgz+hNrU4Oz9EtcROQaTjmGUpAOuyXL2P+ew= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750672143; c=relaxed/simple; bh=TaaWKthcwIdx73b+/7reL8X3rcJ++G0ki23K3IGwN+A=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=L0G9c0Y4xUTdCAGRZJZZWrenk+xriJ19yZ1KYRZca7Un82SnkNGZjh7h0mVWDd5jYM+OZn5mlKRX3Fw6Zb/fu9Z4CDWHExPTCSoe/nPG0H39D+ZPMny1mWsuIpgekFjZ3gkFmcnGdbT2sxjRSIsy5TgkV/hZ/+00/taR39EW8O8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TBmt5pcU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TBmt5pcU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 224FAC4CEF0; Mon, 23 Jun 2025 09:48:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750672143; bh=TaaWKthcwIdx73b+/7reL8X3rcJ++G0ki23K3IGwN+A=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=TBmt5pcUR3SlIILLQ8euRewOvfxBFCn0vS31cjfsa7/rsXDcsjq9IfnqGi4oymE/W YX6OmMU9reh8MQ38oZdEZcw1HGHyg+YohYZnigDtPxoRVca/KGGyoxdA6rgyQxXHxR Z0Eagwb+VrQ/kPw7S22oL4oOjVTbI8Z+g/8ek24uysiK596I6T9KDWx6QUEJVxAodt 0J62+7i+XRVJ061xMEjpeE0/iou4ndK+34WNGBmcdmKzZMN6bpMhic9eWsV2WMtwhk V+29R1SbjQk0lUi2LlNZjCCoLQ+LU7g8JCMr9vWeNA4nyrxVGALMPl2dxJ0XXF7T4O yRjpOWH0fOYOw== Message-ID: <868b20f0-c1ff-4cd7-91bc-e73069aafa95@kernel.org> Date: Mon, 23 Jun 2025 11:48:57 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/13] dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings To: =?UTF-8?Q?Cl=C3=A9ment_Le_Goffic?= , Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-clk@vger.kernel.org References: <20250623-ddrperfm-upstream-v1-0-7dffff168090@foss.st.com> <20250623-ddrperfm-upstream-v1-5-7dffff168090@foss.st.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 23/06/2025 11:27, Clément Le Goffic wrote: > DDRPERFM is the DDR Performance Monitor embedded in STM32MPU SoC. > It allows to monitor DDR events that come from the DDR Controller > such as read or write events. > A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > Signed-off-by: Clément Le Goffic > --- > .../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 93 ++++++++++++++++++++++ > 1 file changed, 93 insertions(+) > > diff --git a/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml > new file mode 100644 > index 000000000000..35d34782865b > --- /dev/null > +++ b/Documentation/devicetree/bindings/perf/st,stm32-ddr-pmu.yaml > @@ -0,0 +1,93 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/perf/st,stm32-ddr-pmu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +maintainers: > + - Clément Le Goffic > + > +title: STMicroelectronics STM32 DDR Performance Monitor (DDRPERFM) > + > +properties: > + compatible: > + enum: > + - st,stm32mp131-ddr-pmu > + - st,stm32mp151-ddr-pmu These are compatible, aren't they? > + - st,stm32mp251-ddr-pmu > + > + reg: > + maxItems: 1 > + > + clocks: > + description: Reference clock for the DDR Performance Monitor Drop description, obvious. > + maxItems: 1 > + > + resets: > + description: Reset control for the DDR Performance Monitor Drop description, obvious. > + maxItems: 1 > + > + access-controllers: > + minItems: 1 > + maxItems: 2 > + > + st,dram-type: > + description: | > + This property is used to specify the type of DRAM memory connected to the > + associated memory controller. It is required for the DDR Performance Monitor > + to correctly interpret the performance data. > + 0 = LPDDR4, > + 1 = LPDDR3, > + 2 = DDR4, > + 3 = DDR3 > + $ref: /schemas/types.yaml#/definitions/uint32 No, use standard JEDEC memory bindings (memory controllers) if you need to describe the memory, otherwise you duplicate that binding and duplicate the memory information. > + enum: [0, 1, 2, 3] > + > +required: > + - compatible > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - st,stm32mp131-ddr-pmu > + - st,stm32mp151-ddr-pmu > + then: > + required: > + - clocks > + - resets > + > + - if: > + properties: > + compatible: > + contains: > + const: st,stm32mp251-ddr-pmu > + then: > + required: > + - access-controllers > + - st,dram-type > + > +additionalProperties: false Best regards, Krzysztof